1 /*
2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <arch_helpers.h>
11 #include <bl31/bl31.h>
12 #include <common/debug.h>
13 #include <drivers/console.h>
14 #include <drivers/delay_timer.h>
15 #include <lib/mmio.h>
16 #include <platform.h>
17 #include <platform_def.h>
18 #include <pmu.h>
19
20 #include <plat_pm_helpers.h>
21 #include <plat_private.h>
22 #include <pm_pd_regs.h>
23 #include <soc.h>
24
25 #define WMSK_VAL 0xffff0000
26
27 static struct reg_region qos_reg_rgns[] = {
28 [QOS_ISP0_MWO] = REG_REGION(0x08, 0x18, 4, 0xfdf40500, 0),
29 [QOS_ISP0_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf40400, 0),
30 [QOS_ISP1_MWO] = REG_REGION(0x08, 0x18, 4, 0xfdf41000, 0),
31 [QOS_ISP1_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf41100, 0),
32 [QOS_VICAP_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf40600, 0),
33 [QOS_VICAP_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf40800, 0),
34 [QOS_FISHEYE0] = REG_REGION(0x08, 0x18, 4, 0xfdf40000, 0),
35 [QOS_FISHEYE1] = REG_REGION(0x08, 0x18, 4, 0xfdf40200, 0),
36 [QOS_VOP_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf82000, 0),
37 [QOS_VOP_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf82200, 0),
38 [QOS_RKVDEC0] = REG_REGION(0x08, 0x18, 4, 0xfdf62000, 0),
39 [QOS_RKVDEC1] = REG_REGION(0x08, 0x18, 4, 0xfdf63000, 0),
40 [QOS_AV1] = REG_REGION(0x08, 0x18, 4, 0xfdf64000, 0),
41 [QOS_RKVENC0_M0RO] = REG_REGION(0x08, 0x18, 4, 0xfdf60000, 0),
42 [QOS_RKVENC0_M1RO] = REG_REGION(0x08, 0x18, 4, 0xfdf60200, 0),
43 [QOS_RKVENC0_M2WO] = REG_REGION(0x08, 0x18, 4, 0xfdf60400, 0),
44 [QOS_RKVENC1_M0RO] = REG_REGION(0x08, 0x18, 4, 0xfdf61000, 0),
45 [QOS_RKVENC1_M1RO] = REG_REGION(0x08, 0x18, 4, 0xfdf61200, 0),
46 [QOS_RKVENC1_M2WO] = REG_REGION(0x08, 0x18, 4, 0xfdf61400, 0),
47 [QOS_DSU_M0] = REG_REGION(0x08, 0x18, 4, 0xfe008000, 0),
48 [QOS_DSU_M1] = REG_REGION(0x08, 0x18, 4, 0xfe008800, 0),
49 [QOS_DSU_MP] = REG_REGION(0x08, 0x18, 4, 0xfdf34200, 0),
50 [QOS_DEBUG] = REG_REGION(0x08, 0x18, 4, 0xfdf34400, 0),
51 [QOS_GPU_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf35000, 0),
52 [QOS_GPU_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf35200, 0),
53 [QOS_GPU_M2] = REG_REGION(0x08, 0x18, 4, 0xfdf35400, 0),
54 [QOS_GPU_M3] = REG_REGION(0x08, 0x18, 4, 0xfdf35600, 0),
55 [QOS_NPU1] = REG_REGION(0x08, 0x18, 4, 0xfdf70000, 0),
56 [QOS_NPU0_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf72200, 0),
57 [QOS_NPU2] = REG_REGION(0x08, 0x18, 4, 0xfdf71000, 0),
58 [QOS_NPU0_MWR] = REG_REGION(0x08, 0x18, 4, 0xfdf72000, 0),
59 [QOS_MCU_NPU] = REG_REGION(0x08, 0x18, 4, 0xfdf72400, 0),
60 [QOS_JPEG_DEC] = REG_REGION(0x08, 0x18, 4, 0xfdf66200, 0),
61 [QOS_JPEG_ENC0] = REG_REGION(0x08, 0x18, 4, 0xfdf66400, 0),
62 [QOS_JPEG_ENC1] = REG_REGION(0x08, 0x18, 4, 0xfdf66600, 0),
63 [QOS_JPEG_ENC2] = REG_REGION(0x08, 0x18, 4, 0xfdf66800, 0),
64 [QOS_JPEG_ENC3] = REG_REGION(0x08, 0x18, 4, 0xfdf66a00, 0),
65 [QOS_RGA2_MRO] = REG_REGION(0x08, 0x18, 4, 0xfdf66c00, 0),
66 [QOS_RGA2_MWO] = REG_REGION(0x08, 0x18, 4, 0xfdf66e00, 0),
67 [QOS_RGA3_0] = REG_REGION(0x08, 0x18, 4, 0xfdf67000, 0),
68 [QOS_RGA3_1] = REG_REGION(0x08, 0x18, 4, 0xfdf36000, 0),
69 [QOS_VDPU] = REG_REGION(0x08, 0x18, 4, 0xfdf67200, 0),
70 [QOS_IEP] = REG_REGION(0x08, 0x18, 4, 0xfdf66000, 0),
71 [QOS_HDCP0] = REG_REGION(0x08, 0x18, 4, 0xfdf80000, 0),
72 [QOS_HDCP1] = REG_REGION(0x08, 0x18, 4, 0xfdf81000, 0),
73 [QOS_HDMIRX] = REG_REGION(0x08, 0x18, 4, 0xfdf81200, 0),
74 [QOS_GIC600_M0] = REG_REGION(0x08, 0x18, 4, 0xfdf3a000, 0),
75 [QOS_GIC600_M1] = REG_REGION(0x08, 0x18, 4, 0xfdf3a200, 0),
76 [QOS_MMU600PCIE_TCU] = REG_REGION(0x08, 0x18, 4, 0xfdf3a400, 0),
77 [QOS_MMU600PHP_TBU] = REG_REGION(0x08, 0x18, 4, 0xfdf3a600, 0),
78 [QOS_MMU600PHP_TCU] = REG_REGION(0x08, 0x18, 4, 0xfdf3a800, 0),
79 [QOS_USB3_0] = REG_REGION(0x08, 0x18, 4, 0xfdf3e200, 0),
80 [QOS_USB3_1] = REG_REGION(0x08, 0x18, 4, 0xfdf3e000, 0),
81 [QOS_USBHOST_0] = REG_REGION(0x08, 0x18, 4, 0xfdf3e400, 0),
82 [QOS_USBHOST_1] = REG_REGION(0x08, 0x18, 4, 0xfdf3e600, 0),
83 [QOS_EMMC] = REG_REGION(0x08, 0x18, 4, 0xfdf38200, 0),
84 [QOS_FSPI] = REG_REGION(0x08, 0x18, 4, 0xfdf38000, 0),
85 [QOS_SDIO] = REG_REGION(0x08, 0x18, 4, 0xfdf39000, 0),
86 [QOS_DECOM] = REG_REGION(0x08, 0x18, 4, 0xfdf32000, 0),
87 [QOS_DMAC0] = REG_REGION(0x08, 0x18, 4, 0xfdf32200, 0),
88 [QOS_DMAC1] = REG_REGION(0x08, 0x18, 4, 0xfdf32400, 0),
89 [QOS_DMAC2] = REG_REGION(0x08, 0x18, 4, 0xfdf32600, 0),
90 [QOS_GIC600M] = REG_REGION(0x08, 0x18, 4, 0xfdf32800, 0),
91 [QOS_DMA2DDR] = REG_REGION(0x08, 0x18, 4, 0xfdf52000, 0),
92 [QOS_MCU_DDR] = REG_REGION(0x08, 0x18, 4, 0xfdf52200, 0),
93 [QOS_VAD] = REG_REGION(0x08, 0x18, 4, 0xfdf3b200, 0),
94 [QOS_MCU_PMU] = REG_REGION(0x08, 0x18, 4, 0xfdf3b000, 0),
95 [QOS_CRYPTOS] = REG_REGION(0x08, 0x18, 4, 0xfdf3d200, 0),
96 [QOS_CRYPTONS] = REG_REGION(0x08, 0x18, 4, 0xfdf3d000, 0),
97 [QOS_DCF] = REG_REGION(0x08, 0x18, 4, 0xfdf3d400, 0),
98 [QOS_SDMMC] = REG_REGION(0x08, 0x18, 4, 0xfdf3d800, 0),
99 };
100
101 static struct reg_region pd_crypto_reg_rgns[] = {
102 /* SECURE CRU */
103 REG_REGION(0x300, 0x30c, 4, SCRU_BASE, WMSK_VAL),
104 REG_REGION(0x800, 0x80c, 4, SCRU_BASE, WMSK_VAL),
105 REG_REGION(0xa00, 0xa0c, 4, SCRU_BASE, WMSK_VAL),
106 REG_REGION(0xd00, 0xd20, 8, SCRU_BASE, 0),
107 REG_REGION(0xd04, 0xd24, 8, SCRU_BASE, WMSK_VAL),
108
109 /* S TIMER0 6 channel */
110 REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x00, 0),
111 REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x00, 0),
112 REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x20, 0),
113 REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x20, 0),
114 REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x40, 0),
115 REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x40, 0),
116 REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x60, 0),
117 REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x60, 0),
118 REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0x80, 0),
119 REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0x80, 0),
120 REG_REGION(0x00, 0x04, 4, STIMER0_BASE + 0xa0, 0),
121 REG_REGION(0x10, 0x10, 4, STIMER0_BASE + 0xa0, 0),
122
123 /* S TIMER1 6 channel */
124 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x00, 0),
125 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x00, 0),
126 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x20, 0),
127 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x20, 0),
128 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x40, 0),
129 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x40, 0),
130 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x60, 0),
131 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x60, 0),
132 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x80, 0),
133 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x80, 0),
134 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0xa0, 0),
135 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0xa0, 0),
136
137 /* wdt_s */
138 REG_REGION(0x04, 0x04, 4, WDT_S_BASE, 0),
139 REG_REGION(0x00, 0x00, 4, WDT_S_BASE, 0),
140 };
141
142 static struct reg_region pd_dsu_reg_rgns[] = {
143 /* dsucru */
144 REG_REGION(0x040, 0x054, 4, DSUCRU_BASE, WMSK_VAL),
145 REG_REGION(0x300, 0x31c, 4, DSUCRU_BASE, WMSK_VAL),
146 REG_REGION(0x800, 0x80c, 4, DSUCRU_BASE, WMSK_VAL),
147 REG_REGION(0xa00, 0xa0c, 4, DSUCRU_BASE, WMSK_VAL),
148 REG_REGION(0xd00, 0xd20, 8, DSUCRU_BASE, 0),
149 REG_REGION(0xd04, 0xd24, 8, DSUCRU_BASE, WMSK_VAL),
150 REG_REGION(0xf00, 0xf00, 4, DSUCRU_BASE, WMSK_VAL),
151 REG_REGION(0xf10, 0xf1c, 4, DSUCRU_BASE, 0),
152
153 /* bcore0cru */
154 REG_REGION(0x000, 0x014, 4, BIGCORE0CRU_BASE, WMSK_VAL),
155 REG_REGION(0x300, 0x304, 4, BIGCORE0CRU_BASE, WMSK_VAL),
156 REG_REGION(0x800, 0x804, 4, BIGCORE0CRU_BASE, WMSK_VAL),
157 REG_REGION(0xa00, 0xa04, 4, BIGCORE0CRU_BASE, WMSK_VAL),
158 REG_REGION(0xcc0, 0xcc4, 4, BIGCORE0CRU_BASE, 0),
159 REG_REGION(0xd00, 0xd00, 4, BIGCORE0CRU_BASE, 0),
160 REG_REGION(0xd04, 0xd04, 4, BIGCORE0CRU_BASE, WMSK_VAL),
161
162 /* bcore1cru */
163 REG_REGION(0x020, 0x034, 4, BIGCORE1CRU_BASE, WMSK_VAL),
164 REG_REGION(0x300, 0x304, 4, BIGCORE1CRU_BASE, WMSK_VAL),
165 REG_REGION(0x800, 0x804, 4, BIGCORE1CRU_BASE, WMSK_VAL),
166 REG_REGION(0xa00, 0xa04, 4, BIGCORE1CRU_BASE, WMSK_VAL),
167 REG_REGION(0xcc0, 0xcc4, 4, BIGCORE1CRU_BASE, 0),
168 REG_REGION(0xd00, 0xd00, 4, BIGCORE1CRU_BASE, 0),
169 REG_REGION(0xd04, 0xd04, 4, BIGCORE1CRU_BASE, WMSK_VAL),
170
171 /* dsugrf */
172 REG_REGION(0x00, 0x18, 4, DSUGRF_BASE, WMSK_VAL),
173 REG_REGION(0x20, 0x20, 4, DSUGRF_BASE, WMSK_VAL),
174 REG_REGION(0x28, 0x30, 4, DSUGRF_BASE, WMSK_VAL),
175 REG_REGION(0x38, 0x38, 4, DSUGRF_BASE, WMSK_VAL),
176
177 /* lcore_grf */
178 REG_REGION(0x20, 0x20, 4, LITCOREGRF_BASE, WMSK_VAL),
179 REG_REGION(0x28, 0x30, 4, LITCOREGRF_BASE, WMSK_VAL),
180
181 /* bcore0_grf */
182 REG_REGION(0x20, 0x20, 4, BIGCORE0GRF_BASE, WMSK_VAL),
183 REG_REGION(0x28, 0x30, 4, BIGCORE0GRF_BASE, WMSK_VAL),
184
185 /* bcore1_grf */
186 REG_REGION(0x20, 0x20, 4, BIGCORE1GRF_BASE, WMSK_VAL),
187 REG_REGION(0x28, 0x28, 4, BIGCORE1GRF_BASE, WMSK_VAL),
188 };
189
190 static struct reg_region pd_php_reg_rgns[] = {
191 /* php_grf */
192 REG_REGION(0x000, 0x008, 4, PHPGRF_BASE, WMSK_VAL),
193 REG_REGION(0x014, 0x024, 4, PHPGRF_BASE, WMSK_VAL),
194 REG_REGION(0x028, 0x02c, 4, PHPGRF_BASE, 0),
195 REG_REGION(0x030, 0x03c, 4, PHPGRF_BASE, WMSK_VAL),
196 REG_REGION(0x05c, 0x060, 4, PHPGRF_BASE, WMSK_VAL),
197 REG_REGION(0x064, 0x068, 4, PHPGRF_BASE, 0),
198 REG_REGION(0x070, 0x070, 4, PHPGRF_BASE, WMSK_VAL),
199 REG_REGION(0x074, 0x0d0, 4, PHPGRF_BASE, 0),
200 REG_REGION(0x0d4, 0x0d4, 4, PHPGRF_BASE, WMSK_VAL),
201 REG_REGION(0x0e0, 0x0e0, 4, PHPGRF_BASE, 0),
202 REG_REGION(0x0e4, 0x0ec, 4, PHPGRF_BASE, WMSK_VAL),
203 REG_REGION(0x100, 0x104, 4, PHPGRF_BASE, WMSK_VAL),
204 REG_REGION(0x10c, 0x130, 4, PHPGRF_BASE, 0),
205 REG_REGION(0x138, 0x138, 4, PHPGRF_BASE, WMSK_VAL),
206 REG_REGION(0x144, 0x168, 4, PHPGRF_BASE, 0),
207 REG_REGION(0x16c, 0x174, 4, PHPGRF_BASE, WMSK_VAL),
208
209 /* php_cru */
210 REG_REGION(0x200, 0x218, 4, PHP_CRU_BASE, WMSK_VAL),
211 REG_REGION(0x800, 0x800, 4, PHP_CRU_BASE, WMSK_VAL),
212 REG_REGION(0xa00, 0xa00, 4, PHP_CRU_BASE, WMSK_VAL),
213
214 /* pcie3phy_grf_cmn_con0 */
215 REG_REGION(0x00, 0x00, 4, PCIE3PHYGRF_BASE, WMSK_VAL),
216 };
217
qos_save(void)218 void qos_save(void)
219 {
220 uint32_t pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0));
221
222 if ((pmu_pd_st0 & BIT(PD_GPU)) == 0) {
223 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M0], 1);
224 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M1], 1);
225 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M2], 1);
226 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GPU_M3], 1);
227 }
228
229 if ((pmu_pd_st0 & BIT(PD_NPU1)) == 0)
230 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU1], 1);
231 if ((pmu_pd_st0 & BIT(PD_NPU2)) == 0)
232 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU2], 1);
233 if ((pmu_pd_st0 & BIT(PD_NPUTOP)) == 0) {
234 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU0_MRO], 1);
235 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_NPU0_MWR], 1);
236 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MCU_NPU], 1);
237 }
238
239 if ((pmu_pd_st0 & BIT(PD_RKVDEC1)) == 0)
240 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVDEC1], 1);
241 if ((pmu_pd_st0 & BIT(PD_RKVDEC0)) == 0)
242 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVDEC0], 1);
243
244 if ((pmu_pd_st0 & BIT(PD_VENC1)) == 0) {
245 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC1_M0RO], 1);
246 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC1_M1RO], 1);
247 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC1_M2WO], 1);
248 }
249 if ((pmu_pd_st0 & BIT(PD_VENC0)) == 0) {
250 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC0_M0RO], 1);
251 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC0_M1RO], 1);
252 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RKVENC0_M2WO], 1);
253 }
254
255 if ((pmu_pd_st0 & BIT(PD_RGA30)) == 0)
256 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA3_0], 1);
257 if ((pmu_pd_st0 & BIT(PD_AV1)) == 0)
258 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_AV1], 1);
259 if ((pmu_pd_st0 & BIT(PD_VDPU)) == 0) {
260 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_DEC], 1);
261 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC0], 1);
262 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC1], 1);
263 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC2], 1);
264 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_JPEG_ENC3], 1);
265 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA2_MRO], 1);
266 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA2_MWO], 1);
267 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VDPU], 1);
268 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_IEP], 1);
269 }
270
271 if ((pmu_pd_st0 & BIT(PD_VO0)) == 0)
272 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_HDCP0], 1);
273 if ((pmu_pd_st0 & BIT(PD_VO1)) == 0) {
274 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_HDCP1], 1);
275 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_HDMIRX], 1);
276 }
277 if ((pmu_pd_st0 & BIT(PD_VOP)) == 0) {
278 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VOP_M0], 1);
279 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VOP_M1], 1);
280 }
281
282 if ((pmu_pd_st0 & BIT(PD_FEC)) == 0) {
283 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_FISHEYE0], 1);
284 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_FISHEYE1], 1);
285 }
286 if ((pmu_pd_st0 & BIT(PD_ISP1)) == 0) {
287 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP1_MWO], 1);
288 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP1_MRO], 1);
289 }
290 if ((pmu_pd_st0 & BIT(PD_VI)) == 0) {
291 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP0_MWO], 1);
292 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_ISP0_MRO], 1);
293 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VICAP_M0], 1);
294 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_VICAP_M1], 1);
295 }
296
297 if ((pmu_pd_st0 & BIT(PD_RGA31)) == 0)
298 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_RGA3_1], 1);
299
300 if ((pmu_pd_st0 & BIT(PD_USB)) == 0) {
301 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USB3_0], 1);
302 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USB3_1], 1);
303 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USBHOST_0], 1);
304 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_USBHOST_1], 1);
305 }
306
307 if ((pmu_pd_st0 & BIT(PD_PHP)) == 0) {
308 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GIC600_M0], 1);
309 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_GIC600_M1], 1);
310 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MMU600PCIE_TCU], 1);
311 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MMU600PHP_TBU], 1);
312 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_MMU600PHP_TCU], 1);
313 }
314
315 if ((pmu_pd_st0 & BIT(PD_SDIO)) == 0)
316 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_SDIO], 1);
317 if ((pmu_pd_st0 & BIT(PD_NVM0)) == 0) {
318 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_FSPI], 1);
319 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_EMMC], 1);
320 }
321
322 if ((pmu_pd_st0 & BIT(PD_SDMMC)) == 0)
323 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_SDMMC], 1);
324
325 if ((pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) {
326 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_CRYPTONS], 1);
327 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_CRYPTOS], 1);
328 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DCF], 1);
329 }
330
331 /* PD_DSU */
332 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DSU_M0], 1);
333 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DSU_M1], 1);
334 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DSU_MP], 1);
335 rockchip_reg_rgn_save(&qos_reg_rgns[QOS_DEBUG], 1);
336 }
337
qos_restore(void)338 void qos_restore(void)
339 {
340 uint32_t pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0));
341
342 if ((pmu_pd_st0 & BIT(PD_GPU)) == 0) {
343 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M0], 1);
344 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M1], 1);
345 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M2], 1);
346 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GPU_M3], 1);
347 }
348
349 if ((pmu_pd_st0 & BIT(PD_NPU1)) == 0)
350 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU1], 1);
351 if ((pmu_pd_st0 & BIT(PD_NPU2)) == 0)
352 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU2], 1);
353 if ((pmu_pd_st0 & BIT(PD_NPUTOP)) == 0) {
354 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU0_MRO], 1);
355 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_NPU0_MWR], 1);
356 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MCU_NPU], 1);
357 }
358
359 if ((pmu_pd_st0 & BIT(PD_RKVDEC1)) == 0)
360 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVDEC1], 1);
361 if ((pmu_pd_st0 & BIT(PD_RKVDEC0)) == 0)
362 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVDEC0], 1);
363
364 if ((pmu_pd_st0 & BIT(PD_VENC1)) == 0) {
365 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC1_M0RO], 1);
366 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC1_M1RO], 1);
367 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC1_M2WO], 1);
368 }
369 if ((pmu_pd_st0 & BIT(PD_VENC0)) == 0) {
370 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC0_M0RO], 1);
371 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC0_M1RO], 1);
372 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RKVENC0_M2WO], 1);
373 }
374
375 if ((pmu_pd_st0 & BIT(PD_RGA30)) == 0)
376 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA3_0], 1);
377 if ((pmu_pd_st0 & BIT(PD_AV1)) == 0)
378 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_AV1], 1);
379 if ((pmu_pd_st0 & BIT(PD_VDPU)) == 0) {
380 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_DEC], 1);
381 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC0], 1);
382 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC1], 1);
383 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC2], 1);
384 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_JPEG_ENC3], 1);
385 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA2_MRO], 1);
386 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA2_MWO], 1);
387 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VDPU], 1);
388 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_IEP], 1);
389 }
390
391 if ((pmu_pd_st0 & BIT(PD_VO0)) == 0)
392 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_HDCP0], 1);
393 if ((pmu_pd_st0 & BIT(PD_VO1)) == 0) {
394 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_HDCP1], 1);
395 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_HDMIRX], 1);
396 }
397 if ((pmu_pd_st0 & BIT(PD_VOP)) == 0) {
398 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VOP_M0], 1);
399 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VOP_M1], 1);
400 }
401
402 if ((pmu_pd_st0 & BIT(PD_FEC)) == 0) {
403 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_FISHEYE0], 1);
404 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_FISHEYE1], 1);
405 }
406 if ((pmu_pd_st0 & BIT(PD_ISP1)) == 0) {
407 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP1_MWO], 1);
408 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP1_MRO], 1);
409 }
410 if ((pmu_pd_st0 & BIT(PD_VI)) == 0) {
411 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP0_MWO], 1);
412 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_ISP0_MRO], 1);
413 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VICAP_M0], 1);
414 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_VICAP_M1], 1);
415 }
416
417 if ((pmu_pd_st0 & BIT(PD_RGA31)) == 0)
418 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_RGA3_1], 1);
419
420 if ((pmu_pd_st0 & BIT(PD_USB)) == 0) {
421 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USB3_0], 1);
422 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USB3_1], 1);
423 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USBHOST_0], 1);
424 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_USBHOST_1], 1);
425 }
426
427 if ((pmu_pd_st0 & BIT(PD_PHP)) == 0) {
428 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GIC600_M0], 1);
429 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_GIC600_M1], 1);
430 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MMU600PCIE_TCU], 1);
431 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MMU600PHP_TBU], 1);
432 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_MMU600PHP_TCU], 1);
433 }
434
435 if ((pmu_pd_st0 & BIT(PD_SDIO)) == 0)
436 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_SDIO], 1);
437 if ((pmu_pd_st0 & BIT(PD_NVM0)) == 0) {
438 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_FSPI], 1);
439 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_EMMC], 1);
440 }
441
442 if ((pmu_pd_st0 & BIT(PD_SDMMC)) == 0)
443 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_SDMMC], 1);
444
445 if ((pmu_pd_st0 & BIT(PD_CRYPTO)) == 0) {
446 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_CRYPTONS], 1);
447 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_CRYPTOS], 1);
448 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DCF], 1);
449 }
450
451 /* PD_DSU */
452 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DSU_M0], 1);
453 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DSU_M1], 1);
454 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DSU_MP], 1);
455 rockchip_reg_rgn_restore(&qos_reg_rgns[QOS_DEBUG], 1);
456 }
457
pd_crypto_save(void)458 void pd_crypto_save(void)
459 {
460 rockchip_reg_rgn_save(pd_crypto_reg_rgns, ARRAY_SIZE(pd_crypto_reg_rgns));
461 }
462
pd_crypto_restore(void)463 void pd_crypto_restore(void)
464 {
465 rockchip_reg_rgn_restore(pd_crypto_reg_rgns, ARRAY_SIZE(pd_crypto_reg_rgns));
466 }
467
468 static uint32_t b0_cru_mode;
469 static uint32_t b1_cru_mode;
470 static uint32_t dsu_cru_mode;
471 static uint32_t bcore0_cru_sel_con2, bcore1_cru_sel_con2;
472
pd_dsu_core_save(void)473 void pd_dsu_core_save(void)
474 {
475 b0_cru_mode = mmio_read_32(BIGCORE0CRU_BASE + 0x280);
476 b1_cru_mode = mmio_read_32(BIGCORE1CRU_BASE + 0x280);
477 dsu_cru_mode = mmio_read_32(DSUCRU_BASE + 0x280);
478 bcore0_cru_sel_con2 = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2));
479 bcore1_cru_sel_con2 = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2));
480
481 rockchip_reg_rgn_save(pd_dsu_reg_rgns, ARRAY_SIZE(pd_dsu_reg_rgns));
482 }
483
pd_dsu_core_restore(void)484 void pd_dsu_core_restore(void)
485 {
486 /* switch bcore0/1 pclk root to 24M */
487 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2),
488 BITS_WITH_WMASK(2, 0x3, 0));
489 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2),
490 BITS_WITH_WMASK(2, 0x3, 0));
491
492 /* slow mode */
493 mmio_write_32(BIGCORE0CRU_BASE + 0x280, 0x00030000);
494 mmio_write_32(BIGCORE1CRU_BASE + 0x280, 0x00030000);
495 mmio_write_32(DSUCRU_BASE + 0x280, 0x00030000);
496
497 rockchip_reg_rgn_restore(pd_dsu_reg_rgns, ARRAY_SIZE(pd_dsu_reg_rgns));
498
499 /* trigger dsu/lcore/bcore mem_cfg */
500 mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(1, 0x1, 14));
501 mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5));
502 mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5));
503 mmio_write_32(BIGCORE1GRF_BASE + 0x30, BITS_WITH_WMASK(1, 0x1, 5));
504 udelay(1);
505 mmio_write_32(DSUGRF_BASE + 0x18, BITS_WITH_WMASK(0, 0x1, 14));
506 mmio_write_32(LITCOREGRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5));
507 mmio_write_32(BIGCORE0GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5));
508 mmio_write_32(BIGCORE1GRF_BASE + 0x30, BITS_WITH_WMASK(0, 0x1, 5));
509
510 /* wait lock */
511 pm_pll_wait_lock(BIGCORE0CRU_BASE + 0x00);
512 pm_pll_wait_lock(BIGCORE1CRU_BASE + 0x20);
513 pm_pll_wait_lock(DSUCRU_BASE + 0x40);
514
515 /* restore mode */
516 mmio_write_32(BIGCORE0CRU_BASE + 0x280, WITH_16BITS_WMSK(b0_cru_mode));
517 mmio_write_32(BIGCORE1CRU_BASE + 0x280, WITH_16BITS_WMSK(b1_cru_mode));
518 mmio_write_32(DSUCRU_BASE + 0x280, WITH_16BITS_WMSK(dsu_cru_mode));
519
520 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2),
521 WITH_16BITS_WMSK(bcore0_cru_sel_con2));
522 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2),
523 WITH_16BITS_WMSK(bcore1_cru_sel_con2));
524 }
525
526 static uint32_t php_ppll_con0;
527
pd_php_save(void)528 void pd_php_save(void)
529 {
530 php_ppll_con0 = mmio_read_32(PHP_CRU_BASE + 0x200);
531
532 /* php_ppll bypass */
533 mmio_write_32(PHP_CRU_BASE + 0x200, BITS_WITH_WMASK(1u, 1u, 15));
534 dsb();
535 isb();
536 rockchip_reg_rgn_save(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns));
537 }
538
pd_php_restore(void)539 void pd_php_restore(void)
540 {
541 rockchip_reg_rgn_restore(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns));
542
543 pm_pll_wait_lock(PHP_CRU_BASE + 0x200);
544
545 /* restore php_ppll bypass */
546 mmio_write_32(PHP_CRU_BASE + 0x200, WITH_16BITS_WMSK(php_ppll_con0));
547 }
548
pm_reg_rgns_init(void)549 void pm_reg_rgns_init(void)
550 {
551 rockchip_alloc_region_mem(qos_reg_rgns, ARRAY_SIZE(qos_reg_rgns));
552 rockchip_alloc_region_mem(pd_crypto_reg_rgns, ARRAY_SIZE(pd_crypto_reg_rgns));
553 rockchip_alloc_region_mem(pd_dsu_reg_rgns, ARRAY_SIZE(pd_dsu_reg_rgns));
554 rockchip_alloc_region_mem(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns));
555 }
556