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1 /*
2  * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <lib/mmio.h>
9 
10 #include <platform_def.h>
11 
12 #include <secure.h>
13 #include <soc.h>
14 
secure_fw_master_init(void)15 static void secure_fw_master_init(void)
16 {
17 	uint32_t i;
18 
19 	/* ddr_mcu can access all ddr-regions */
20 	mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(1), 0x0000ffff);
21 	/* dcf/crypto_s can access all ddr-regions */
22 	mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(14), 0x00000000);
23 	/* dsu_mp_sec can access all ddr-regions.
24 	 * DSU access memory [f000_0000~ff00_0000] through MP in firewall_ddr.
25 	 */
26 	mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(36), 0xffff0000);
27 
28 	/* all other ns-master can't access all ddr-regions */
29 	for (i = 0; i < FIREWALL_DDR_MST_CNT; i++) {
30 		if (i == 1 || i == 14 || i == 36)
31 			continue;
32 
33 		mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_MST(i), 0xffffffff);
34 	}
35 
36 	/* mcu_pmu can access all sram-regions */
37 	mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(19), 0x000000ff);
38 	/* dsu mp-sec can access all sram-regions */
39 	mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(38), 0x000000ff);
40 	/* nsp_dsu2main_sec can access all sram-regions */
41 	mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(41), 0x00000000);
42 
43 	/* all ns-master can't access all sram-regions */
44 	for (i = 0; i < FIREWALL_SYSMEM_MST_CNT; i++) {
45 		if (i == 19 || i == 38 || i == 41)
46 			continue;
47 
48 		mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_MST(i),
49 			      0x00ff00ff);
50 	}
51 
52 	/* dsu-ns can't access all ddr-regions, dsu-s can access all ddr-regions */
53 	mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(0), 0xffffffff);
54 	mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_MST(1), 0x00000000);
55 	dsb();
56 	isb();
57 }
58 
59 /* unit: Mb */
dsu_fw_rgn_config(uint64_t base_mb,uint64_t top_mb,int rgn_id)60 static void dsu_fw_rgn_config(uint64_t base_mb, uint64_t top_mb, int rgn_id)
61 {
62 	int i;
63 
64 	if (rgn_id >= FIREWALL_DSU_RGN_CNT || rgn_id < 0) {
65 		ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id);
66 		panic();
67 	}
68 
69 	mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(rgn_id),
70 		      RG_MAP_SECURE(top_mb, base_mb));
71 
72 	for (i = 0; i < DDR_CHN_CNT; i++)
73 		mmio_setbits_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i),
74 				BIT(rgn_id));
75 }
76 
77 /* unit: Mb */
ddr_fw_rgn_config(uint64_t base_mb,uint64_t top_mb,int rgn_id)78 static void ddr_fw_rgn_config(uint64_t base_mb, uint64_t top_mb, int rgn_id)
79 {
80 	if (rgn_id >= FIREWALL_DDR_RGN_CNT || rgn_id < 0) {
81 		ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id);
82 		panic();
83 	}
84 
85 	mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_RGN(rgn_id),
86 		      RG_MAP_SECURE(top_mb, base_mb));
87 
88 	/* enable region */
89 	mmio_setbits_32(FIREWALL_DDR_BASE + FIREWALL_DDR_CON,
90 			BIT(rgn_id));
91 }
92 
93 /* Unit: Kb */
sram_fw_rgn_config(uint64_t base_kb,uint64_t top_kb,int rgn_id)94 static void sram_fw_rgn_config(uint64_t base_kb, uint64_t top_kb, int rgn_id)
95 {
96 	if (rgn_id >= FIREWALL_SYSMEM_RGN_CNT || rgn_id < 0) {
97 		ERROR("%s regions-id:%d is invalid!\n", __func__, rgn_id);
98 		panic();
99 	}
100 
101 	mmio_write_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_RGN(rgn_id),
102 		      RG_MAP_SRAM_SECURE(top_kb, base_kb));
103 
104 	/* enable region */
105 	mmio_setbits_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_CON, BIT(rgn_id));
106 }
107 
secure_region_init(void)108 static void secure_region_init(void)
109 {
110 	uint32_t i;
111 
112 	/* disable all region first except region0 */
113 	mmio_clrbits_32(FIREWALL_DDR_BASE + FIREWALL_DDR_CON, 0xfffe);
114 	for (i = 0; i < FIREWALL_DSU_CON_CNT; i++)
115 		mmio_clrbits_32(FIREWALL_DSU_BASE + FIREWALL_DSU_CON(i), 0xfffe);
116 	mmio_clrbits_32(FIREWALL_SYSMEM_BASE + FIREWALL_SYSMEM_CON, 0xfe);
117 
118 	secure_fw_master_init();
119 
120 	/* Use FW_DDR_RGN0_REG to config 0~1M space to secure */
121 	dsu_fw_rgn_config(0, 1, 0);
122 	ddr_fw_rgn_config(0, 1, 0);
123 
124 	/* Use FIREWALL_SYSMEM_RGN0 to config SRAM_ENTRY code(0~4k of sram) to secure */
125 	sram_fw_rgn_config(0, 4, 0);
126 	/* For 0xffff0000~0xffffffff, use FIREWALL_SYSMEM_RGN7 to config
127 	 * 960~1024k of sram to secure.
128 	 */
129 	sram_fw_rgn_config(960, 1024, 7);
130 }
131 
secure_timer_init(void)132 void secure_timer_init(void)
133 {
134 	/* gpu's cntvalue comes from stimer1 channel_5 */
135 	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
136 		      TIMER_DIS);
137 
138 	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT0, 0xffffffff);
139 	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT1, 0xffffffff);
140 
141 	/* auto reload & enable the timer */
142 	mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
143 		      TIMER_EN | TIMER_FMODE);
144 }
145 
sgrf_init(void)146 void sgrf_init(void)
147 {
148 	uint32_t i;
149 
150 	secure_region_init();
151 
152 	/* config master ddr_mcu_prot|dcf_wr|dcf_rd as secure */
153 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(14), 0x001f0011);
154 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(15), 0xffffffff);
155 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(16), 0x03ff03ff);
156 
157 	/* config slave mailbox_mcu_ddr as secure */
158 	mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(4), 0xffff2000);
159 	/* config slave int256mux4_mcu_ddr|int256mux4_mcu_pmu as secure */
160 	mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(5), 0xffff0060);
161 	/* config slave ddrgrf*|dma2ddr|ddrphy*_cru|umctl* as secure */
162 	mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(24), 0xffff0fbf);
163 	/* config slave ddrphy*|ddr_stanby*|ddr_mcu_timer|ddr_mcu_wdt as secure */
164 	mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(25), 0xffff03ff);
165 
166 	/* config all other slave as ns */
167 	for (i = 0; i < SGRF_FIREWALL_CON_CNT; i++) {
168 		if (i == 4 || i == 5 || i == 24 || i == 25)
169 			continue;
170 
171 		mmio_write_32(BUSSGRF_BASE + SGRF_FIREWALL_CON(i), 0xffff0000);
172 	}
173 
174 	/* config vad_hprot non-secure, pmu_mcu_hprot as secure */
175 	mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00180010);
176 	/* config pmu1, pmu0, pmu_sram as secure */
177 	mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(1), 0xefbe6020);
178 	/* config remap_pmu_mem, h_pmu_mem as secure */
179 	mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(2), 0x01f900c0);
180 
181 	/* disable dp encryption */
182 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(13), 0x00180018);
183 
184 	/* select grf config for pcie ats */
185 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(17), 0x11111111);
186 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(18), 0x11111111);
187 	mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(19), 0x00110011);
188 }
189