1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <bl31/interrupt_mgmt.h>
15 #include <drivers/console.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17
18 #include <rpi_hw.h>
19 #include <rpi_shared.h>
20
21 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
22 DEVICE0_SIZE, \
23 MT_DEVICE | MT_RW | MT_SECURE)
24
25 #ifdef SHARED_RAM_BASE
26 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
27 SHARED_RAM_SIZE, \
28 MT_DEVICE | MT_RW | MT_SECURE)
29 #endif
30
31 #ifdef RPI3_PRELOADED_DTB_BASE
32 #define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
33 MT_MEMORY | MT_RW | MT_NS)
34 #endif
35
36 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
37 MT_MEMORY | MT_RW | MT_NS)
38
39 #define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \
40 PLAT_RPI3_FIP_MAX_SIZE, \
41 MT_MEMORY | MT_RO | MT_NS)
42
43 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
44 MT_MEMORY | MT_RW | MT_SECURE)
45
46 #ifdef SPD_opteed
47 #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
48 RPI3_OPTEE_PAGEABLE_LOAD_BASE, \
49 RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \
50 MT_MEMORY | MT_RW | MT_SECURE)
51 #endif
52
53 /*
54 * Table of regions for various BL stages to map using the MMU.
55 */
56 #ifdef IMAGE_BL1
57 static const mmap_region_t plat_rpi3_mmap[] = {
58 #ifdef MAP_SHARED_RAM
59 MAP_SHARED_RAM,
60 #endif
61 MAP_DEVICE0,
62 MAP_FIP,
63 #ifdef SPD_opteed
64 MAP_OPTEE_PAGEABLE,
65 #endif
66 {0}
67 };
68 #endif
69
70 #ifdef IMAGE_BL2
71 static const mmap_region_t plat_rpi3_mmap[] = {
72 #ifdef MAP_SHARED_RAM
73 MAP_SHARED_RAM,
74 #endif
75 MAP_DEVICE0,
76 MAP_FIP,
77 MAP_NS_DRAM0,
78 #ifdef BL32_BASE
79 MAP_BL32_MEM,
80 #endif
81 {0}
82 };
83 #endif
84
85 #ifdef IMAGE_BL31
86 static const mmap_region_t plat_rpi3_mmap[] = {
87 #ifdef MAP_SHARED_RAM
88 MAP_SHARED_RAM,
89 #endif
90 MAP_DEVICE0,
91 #ifdef RPI3_PRELOADED_DTB_BASE
92 MAP_NS_DTB,
93 #endif
94 #ifdef BL32_BASE
95 MAP_BL32_MEM,
96 #endif
97 {0}
98 };
99 #endif
100
101 /*******************************************************************************
102 * Function that sets up the console
103 ******************************************************************************/
104 static console_t rpi3_console;
105
rpi3_console_init(void)106 void rpi3_console_init(void)
107 {
108 int console_scope = CONSOLE_FLAG_BOOT;
109 int rc;
110
111 if (RPI3_RUNTIME_UART != -1)
112 console_scope |= CONSOLE_FLAG_RUNTIME;
113
114 rc = rpi3_register_used_uart(&rpi3_console);
115
116 if (rc == 0) {
117 /*
118 * The crash console doesn't use the multi console API, it uses
119 * the core console functions directly. It is safe to call panic
120 * and let it print debug information.
121 */
122 panic();
123 }
124
125 console_set_scope(&rpi3_console, console_scope);
126 }
127
128 /*******************************************************************************
129 * Function that sets up the translation tables.
130 ******************************************************************************/
rpi3_setup_page_tables(uintptr_t total_base,size_t total_size,uintptr_t code_start,uintptr_t code_limit,uintptr_t rodata_start,uintptr_t rodata_limit,uintptr_t coh_start,uintptr_t coh_limit)131 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
132 uintptr_t code_start, uintptr_t code_limit,
133 uintptr_t rodata_start, uintptr_t rodata_limit
134 #if USE_COHERENT_MEM
135 , uintptr_t coh_start, uintptr_t coh_limit
136 #endif
137 )
138 {
139 /*
140 * Map the Trusted SRAM with appropriate memory attributes.
141 * Subsequent mappings will adjust the attributes for specific regions.
142 */
143 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
144 (void *) total_base, (void *) (total_base + total_size));
145 mmap_add_region(total_base, total_base,
146 total_size,
147 MT_MEMORY | MT_RW | MT_SECURE);
148
149 /* Re-map the code section */
150 VERBOSE("Code region: %p - %p\n",
151 (void *) code_start, (void *) code_limit);
152 mmap_add_region(code_start, code_start,
153 code_limit - code_start,
154 MT_CODE | MT_SECURE);
155
156 /* Re-map the read-only data section */
157 VERBOSE("Read-only data region: %p - %p\n",
158 (void *) rodata_start, (void *) rodata_limit);
159 mmap_add_region(rodata_start, rodata_start,
160 rodata_limit - rodata_start,
161 MT_RO_DATA | MT_SECURE);
162
163 #if USE_COHERENT_MEM
164 /* Re-map the coherent memory region */
165 VERBOSE("Coherent region: %p - %p\n",
166 (void *) coh_start, (void *) coh_limit);
167 mmap_add_region(coh_start, coh_start,
168 coh_limit - coh_start,
169 MT_DEVICE | MT_RW | MT_SECURE);
170 #endif
171
172 mmap_add(plat_rpi3_mmap);
173
174 init_xlat_tables();
175 }
176
177 /*******************************************************************************
178 * Gets SPSR for BL32 entry
179 ******************************************************************************/
rpi3_get_spsr_for_bl32_entry(void)180 uint32_t rpi3_get_spsr_for_bl32_entry(void)
181 {
182 /*
183 * The Secure Payload Dispatcher service is responsible for
184 * setting the SPSR prior to entry into the BL32 image.
185 */
186 return 0;
187 }
188
189 /*******************************************************************************
190 * Gets SPSR for BL33 entry
191 ******************************************************************************/
rpi3_get_spsr_for_bl33_entry(void)192 uint32_t rpi3_get_spsr_for_bl33_entry(void)
193 {
194 #if RPI3_BL33_IN_AARCH32
195 INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
196 return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
197 DISABLE_ALL_EXCEPTIONS);
198 #else
199 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
200 #endif
201 }
202
plat_get_syscnt_freq2(void)203 unsigned int plat_get_syscnt_freq2(void)
204 {
205 return SYS_COUNTER_FREQ_IN_TICKS;
206 }
207
plat_ic_get_pending_interrupt_type(void)208 uint32_t plat_ic_get_pending_interrupt_type(void)
209 {
210 ERROR("rpi3: Interrupt routed to EL3.\n");
211 return INTR_TYPE_INVAL;
212 }
213
plat_interrupt_type_to_line(uint32_t type,uint32_t security_state)214 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
215 {
216 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
217 (type == INTR_TYPE_NS));
218
219 assert(sec_state_is_valid(security_state));
220
221 /* Non-secure interrupts are signalled on the IRQ line always. */
222 if (type == INTR_TYPE_NS)
223 return __builtin_ctz(SCR_IRQ_BIT);
224
225 /* Secure interrupts are signalled on the FIQ line always. */
226 return __builtin_ctz(SCR_FIQ_BIT);
227 }
228