1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com> 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/tbbr/tbbr_img_def.h> 13 #include <lib/utils_def.h> 14 #include <plat/common/common_def.h> 15 16 #include "rpi_hw.h" 17 18 /* Special value used to verify platform parameters from BL2 to BL31 */ 19 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) 20 21 #define PLATFORM_STACK_SIZE ULL(0x1000) 22 23 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 24 #define PLATFORM_CLUSTER_COUNT U(1) 25 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 26 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 27 28 #define RPI_PRIMARY_CPU U(0) 29 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 31 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 32 PLATFORM_CORE_COUNT) 33 34 #define PLAT_MAX_RET_STATE U(1) 35 #define PLAT_MAX_OFF_STATE U(2) 36 37 /* Local power state for power domains in Run state. */ 38 #define PLAT_LOCAL_STATE_RUN U(0) 39 /* Local power state for retention. Valid only for CPU power domains */ 40 #define PLAT_LOCAL_STATE_RET U(1) 41 /* 42 * Local power state for OFF/power-down. Valid for CPU and cluster power 43 * domains. 44 */ 45 #define PLAT_LOCAL_STATE_OFF U(2) 46 47 /* 48 * Macros used to parse state information from State-ID if it is using the 49 * recommended encoding for State-ID. 50 */ 51 #define PLAT_LOCAL_PSTATE_WIDTH U(4) 52 #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 53 54 /* 55 * Some data must be aligned on the biggest cache line size in the platform. 56 * This is known only to the platform as it might have a combination of 57 * integrated and external caches. 58 */ 59 #define CACHE_WRITEBACK_SHIFT U(6) 60 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 61 62 /* 63 * I/O registers. 64 */ 65 #define DEVICE0_BASE RPI_IO_BASE 66 #define DEVICE0_SIZE RPI_IO_SIZE 67 68 /* 69 * Mailbox to control the secondary cores. All secondary cores are held in a 70 * wait loop in cold boot. To release them perform the following steps (plus 71 * any additional barriers that may be needed): 72 * 73 * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; 74 * *entrypoint = ADDRESS_TO_JUMP_TO; 75 * 76 * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; 77 * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; 78 * 79 * sev(); 80 */ 81 /* The secure entry point to be used on warm reset by all CPUs. */ 82 #define PLAT_RPI3_TM_ENTRYPOINT 0x100 83 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) 84 85 /* Hold entries for each CPU. */ 86 #define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ 87 PLAT_RPI3_TM_ENTRYPOINT_SIZE) 88 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) 89 #define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ 90 PLATFORM_CORE_COUNT) 91 92 #define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ 93 PLAT_RPI3_TM_HOLD_SIZE) 94 95 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) 96 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) 97 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2) 98 99 /* 100 * BL31 specific defines. 101 * 102 * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the 103 * current BL31 debug size plus a little space for growth. 104 */ 105 #define PLAT_MAX_BL31_SIZE ULL(0x80000) 106 107 #define BL31_BASE ULL(0x1000) 108 #define BL31_LIMIT ULL(0x80000) 109 #define BL31_PROGBITS_LIMIT ULL(0x80000) 110 111 #define SEC_SRAM_ID 0 112 #define SEC_DRAM_ID 1 113 114 /* 115 * Other memory-related defines. 116 */ 117 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) 118 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 119 120 #define MAX_MMAP_REGIONS 8 121 #define MAX_XLAT_TABLES 4 122 123 #define MAX_IO_DEVICES U(3) 124 #define MAX_IO_HANDLES U(4) 125 126 #define MAX_IO_BLOCK_DEVICES U(1) 127 128 /* 129 * Serial-related constants. 130 */ 131 #define PLAT_RPI_PL011_UART_BASE RPI4_PL011_UART_BASE 132 #define PLAT_RPI_PL011_UART_CLOCK RPI4_PL011_UART_CLOCK 133 #define PLAT_RPI_UART_BAUDRATE ULL(115200) 134 #define PLAT_RPI_CRASH_UART_BASE PLAT_RPI_PL011_UART_BASE 135 136 /* 137 * System counter 138 */ 139 #define SYS_COUNTER_FREQ_IN_TICKS ULL(54000000) 140 141 #endif /* PLATFORM_DEF_H */ 142