1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_FIP_DEF_H 8 #define STM32MP1_FIP_DEF_H 9 10 #define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ 11 12 #if TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP 13 #if STM32MP15 14 #define STM32MP_BL2_RO_SIZE U(0x00014000) /* 80 KB */ 15 #define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */ 16 #endif /* STM32MP15 */ 17 #else /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ 18 #if STM32MP13 19 #if BL2_IN_XIP_MEM 20 #define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ 21 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ 22 #else 23 /* STM32MP_BL2_RO_SIZE not used if !BL2_IN_XIP_MEM */ 24 #define STM32MP_BL2_SIZE U(0x0001B000) /* 108KB for BL2 */ 25 /* with 20KB for DTB, SYSRAM is full */ 26 #endif 27 #endif /* STM32MP13 */ 28 #if STM32MP15 29 #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ 30 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ 31 #endif /* STM32MP15 */ 32 #endif /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ 33 34 #if STM32MP13 35 #if TRUSTED_BOARD_BOOT 36 #define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 37 #else /* TRUSTED_BOARD_BOOT */ 38 #define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ 39 #endif /* TRUSTED_BOARD_BOOT */ 40 #endif /* STM32MP13 */ 41 #if STM32MP15 42 #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ 43 #endif /* STM32MP15 */ 44 #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ 45 #define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 46 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */ 47 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */ 48 49 #if STM32MP13 50 #define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \ 51 STM32MP_BL2_DTB_SIZE) 52 #endif /* STM32MP13 */ 53 #if STM32MP15 54 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 55 STM32MP_SEC_SYSRAM_SIZE - \ 56 STM32MP_BL2_SIZE) 57 #endif /* STM32MP15 */ 58 59 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 60 61 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 62 STM32MP_BL2_RO_SIZE) 63 64 #if STM32MP13 65 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 66 STM32MP_SYSRAM_SIZE - \ 67 STM32MP_BL2_RW_BASE) 68 69 #define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE 70 #endif /* STM32MP13 */ 71 #if STM32MP15 72 #define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \ 73 STM32MP_SEC_SYSRAM_SIZE - \ 74 STM32MP_BL2_RW_BASE) 75 76 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 77 STM32MP_BL2_DTB_SIZE) 78 #endif /* STM32MP15 */ 79 80 #define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE 81 82 #define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \ 83 STM32MP_BL32_DTB_SIZE) 84 85 86 #if defined(IMAGE_BL2) 87 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 88 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 89 #endif 90 #if defined(IMAGE_BL32) 91 #define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE 92 #define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE 93 #endif 94 95 #ifdef AARCH32_SP_OPTEE 96 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 97 98 #define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \ 99 STM32MP_OPTEE_BASE) 100 #endif 101 102 #if STM32MP13 103 #define STM32MP_FW_CONFIG_BASE SRAM3_BASE 104 #endif /* STM32MP13 */ 105 #if STM32MP15 106 #define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \ 107 STM32MP_SYSRAM_SIZE - \ 108 PAGE_SIZE) 109 #endif /* STM32MP15 */ 110 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 111 STM32MP_BL33_MAX_SIZE) 112 113 /* 114 * MAX_MMAP_REGIONS is usually: 115 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 116 */ 117 #if defined(IMAGE_BL32) 118 #define MAX_MMAP_REGIONS 10 119 #endif 120 121 #endif /* STM32MP1_FIP_DEF_H */ 122