1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp2_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #define PLATFORM_STACK_SIZE 0xC00 23 24 #define STM32MP_PRIMARY_CPU U(0x0) 25 #define STM32MP_SECONDARY_CPU U(0x1) 26 27 #define MAX_IO_DEVICES U(4) 28 #define MAX_IO_HANDLES U(4) 29 #define MAX_IO_BLOCK_DEVICES U(1) 30 #define MAX_IO_MTD_DEVICES U(1) 31 32 #define PLATFORM_CLUSTER_COUNT U(1) 33 #define PLATFORM_CORE_COUNT U(2) 34 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 35 36 #define PLAT_MAX_PWR_LVL U(1) 37 #define PLAT_MIN_SUSPEND_PWR_LVL U(2) 38 #define PLAT_NUM_PWR_DOMAINS U(6) 39 40 /* Local power state for power domains in Run state. */ 41 #define STM32MP_LOCAL_STATE_RUN U(0) 42 /* Local power state for retention. */ 43 #define STM32MP_LOCAL_STATE_RET U(1) 44 #define STM32MP_LOCAL_STATE_LP U(2) 45 #define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP 46 /* Local power state for OFF/power-down. */ 47 #define STM32MP_LOCAL_STATE_OFF U(3) 48 #define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF 49 50 /* Macros to parse the state information from State-ID (recommended encoding) */ 51 #define PLAT_LOCAL_PSTATE_WIDTH U(4) 52 #define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0) 53 54 /******************************************************************************* 55 * BL2 specific defines. 56 ******************************************************************************/ 57 /* 58 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 59 * size plus a little space for growth. 60 */ 61 #define BL2_BASE STM32MP_BL2_BASE 62 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 63 STM32MP_BL2_SIZE) 64 65 #define BL2_RO_BASE STM32MP_BL2_RO_BASE 66 #define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \ 67 STM32MP_BL2_RO_SIZE) 68 69 #define BL2_RW_BASE STM32MP_BL2_RW_BASE 70 #define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \ 71 STM32MP_BL2_RW_SIZE) 72 73 /******************************************************************************* 74 * BL31 specific defines. 75 ******************************************************************************/ 76 #define BL31_BASE 0 77 #define BL31_LIMIT (STM32MP_SEC_SYSRAM_SIZE / 2) 78 79 /******************************************************************************* 80 * BL33 specific defines. 81 ******************************************************************************/ 82 #define BL33_BASE STM32MP_BL33_BASE 83 84 /******************************************************************************* 85 * Platform specific page table and MMU setup constants 86 ******************************************************************************/ 87 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33) 88 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33) 89 90 /******************************************************************************* 91 * Declarations and constants to access the mailboxes safely. Each mailbox is 92 * aligned on the biggest cache line size in the platform. This is known only 93 * to the platform as it might have a combination of integrated and external 94 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 95 * line at any cache level. They could belong to different cpus/clusters & 96 * get written while being protected by different locks causing corruption of 97 * a valid mailbox address. 98 ******************************************************************************/ 99 #define CACHE_WRITEBACK_SHIFT 6 100 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 101 102 /* 103 * Secure Interrupt: based on the standard ARM mapping 104 */ 105 #define ARM_IRQ_SEC_PHY_TIMER U(29) 106 107 #define ARM_IRQ_NON_SEC_SGI_0 U(0) 108 109 #define ARM_IRQ_SEC_SGI_0 U(8) 110 #define ARM_IRQ_SEC_SGI_1 U(9) 111 #define ARM_IRQ_SEC_SGI_2 U(10) 112 #define ARM_IRQ_SEC_SGI_3 U(11) 113 #define ARM_IRQ_SEC_SGI_4 U(12) 114 #define ARM_IRQ_SEC_SGI_5 U(13) 115 #define ARM_IRQ_SEC_SGI_6 U(14) 116 #define ARM_IRQ_SEC_SGI_7 U(15) 117 118 /* Platform IRQ Priority */ 119 #define STM32MP_IRQ_SEC_SPI_PRIO U(0x10) 120 121 /* 122 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 123 * terminology. On a GICv2 system or mode, the lists will be merged and treated 124 * as Group 0 interrupts. 125 */ 126 #define PLATFORM_G1S_PROPS(grp) \ 127 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 128 GIC_HIGHEST_SEC_PRIORITY, \ 129 (grp), GIC_INTR_CFG_LEVEL), \ 130 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 131 GIC_HIGHEST_SEC_PRIORITY, \ 132 (grp), GIC_INTR_CFG_EDGE), \ 133 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 134 GIC_HIGHEST_SEC_PRIORITY, \ 135 (grp), GIC_INTR_CFG_EDGE), \ 136 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 137 GIC_HIGHEST_SEC_PRIORITY, \ 138 (grp), GIC_INTR_CFG_EDGE), \ 139 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 140 GIC_HIGHEST_SEC_PRIORITY, \ 141 (grp), GIC_INTR_CFG_EDGE), \ 142 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 143 GIC_HIGHEST_SEC_PRIORITY, \ 144 (grp), GIC_INTR_CFG_EDGE), \ 145 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 146 GIC_HIGHEST_SEC_PRIORITY, \ 147 (grp), GIC_INTR_CFG_EDGE) 148 149 #define PLATFORM_G0_PROPS(grp) \ 150 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 151 GIC_HIGHEST_SEC_PRIORITY, \ 152 (grp), GIC_INTR_CFG_EDGE), \ 153 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 154 GIC_HIGHEST_SEC_PRIORITY, \ 155 (grp), GIC_INTR_CFG_EDGE) 156 157 #endif /* PLATFORM_DEF_H */ 158