1/* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <drivers/arm/gicv3.h> 12 13#include <platform_def.h> 14 15 .globl plat_arm_calc_core_pos 16 .globl plat_secondary_cold_boot_setup 17 .globl plat_is_my_cpu_primary 18 .globl platform_mem_init 19 .globl plat_my_core_pos 20 21 /* ----------------------------------------------------- 22 * void plat_secondary_cold_boot_setup (void); 23 * 24 * This function performs any platform specific actions 25 * needed for a secondary cpu after a cold reset e.g 26 * mark the cpu's presence, mechanism to place it in a 27 * holding pen etc. 28 * TODO: Should we read the PSYS register to make sure 29 * that the request has gone through. 30 * ----------------------------------------------------- 31 */ 32func plat_secondary_cold_boot_setup 33 mrs x0, mpidr_el1 34 35 /* 36 * There is no sane reason to come out of this wfi. This 37 * cpu will be powered on and reset by the cpu_on pm api 38 */ 39 dsb sy 40 bl plat_panic_handler 41endfunc plat_secondary_cold_boot_setup 42 43func plat_is_my_cpu_primary 44 mov x9, x30 45 bl plat_my_core_pos 46 cmp x0, #VERSAL_NET_PRIMARY_CPU 47 cset x0, eq 48 ret x9 49endfunc plat_is_my_cpu_primary 50 51 /* ----------------------------------------------------- 52 * unsigned int plat_my_core_pos(void) 53 * This function uses the plat_core_pos_by_mpidr() 54 * definition to get the index of the calling CPU. 55 * ----------------------------------------------------- 56 */ 57func plat_my_core_pos 58 mrs x0, mpidr_el1 59 b plat_core_pos_by_mpidr 60endfunc plat_my_core_pos 61 62 /* ----------------------------------------------------- 63 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 64 * This function uses the plat_core_pos_by_mpidr() 65 * definition to get the index of the calling CPU. 66 * ----------------------------------------------------- 67 */ 68func plat_arm_calc_core_pos 69 b plat_core_pos_by_mpidr 70endfunc plat_arm_calc_core_pos 71 72 /* --------------------------------------------------------------------- 73 * We don't need to carry out any memory initialization on Versal NET 74 * platform. The Secure RAM is accessible straight away. 75 * --------------------------------------------------------------------- 76 */ 77func platform_mem_init 78 ret 79endfunc platform_mem_init 80