1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __MSM_DRM_H__ 8 #define __MSM_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define MSM_PIPE_NONE 0x00 14 #define MSM_PIPE_2D0 0x01 15 #define MSM_PIPE_2D1 0x02 16 #define MSM_PIPE_3D0 0x10 17 #define MSM_PIPE_ID_MASK 0xffff 18 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 19 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 20 struct drm_msm_timespec { 21 __s64 tv_sec; 22 __s64 tv_nsec; 23 }; 24 #define MSM_PARAM_GPU_ID 0x01 25 #define MSM_PARAM_GMEM_SIZE 0x02 26 #define MSM_PARAM_CHIP_ID 0x03 27 #define MSM_PARAM_MAX_FREQ 0x04 28 #define MSM_PARAM_TIMESTAMP 0x05 29 #define MSM_PARAM_GMEM_BASE 0x06 30 #define MSM_PARAM_PRIORITIES 0x07 31 #define MSM_PARAM_PP_PGTABLE 0x08 32 #define MSM_PARAM_FAULTS 0x09 33 #define MSM_PARAM_SUSPENDS 0x0a 34 #define MSM_PARAM_SYSPROF 0x0b 35 #define MSM_PARAM_COMM 0x0c 36 #define MSM_PARAM_CMDLINE 0x0d 37 #define MSM_PARAM_VA_START 0x0e 38 #define MSM_PARAM_VA_SIZE 0x0f 39 #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 40 #define MSM_PARAM_RAYTRACING 0x11 41 #define MSM_PARAM_UBWC_SWIZZLE 0x12 42 #define MSM_PARAM_MACROTILE_MODE 0x13 43 #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 44 struct drm_msm_param { 45 __u32 pipe; 46 __u32 param; 47 __u64 value; 48 __u32 len; 49 __u32 pad; 50 }; 51 #define MSM_BO_SCANOUT 0x00000001 52 #define MSM_BO_GPU_READONLY 0x00000002 53 #define MSM_BO_CACHE_MASK 0x000f0000 54 #define MSM_BO_CACHED 0x00010000 55 #define MSM_BO_WC 0x00020000 56 #define MSM_BO_UNCACHED 0x00040000 57 #define MSM_BO_CACHED_COHERENT 0x080000 58 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHE_MASK) 59 struct drm_msm_gem_new { 60 __u64 size; 61 __u32 flags; 62 __u32 handle; 63 }; 64 #define MSM_INFO_GET_OFFSET 0x00 65 #define MSM_INFO_GET_IOVA 0x01 66 #define MSM_INFO_SET_NAME 0x02 67 #define MSM_INFO_GET_NAME 0x03 68 #define MSM_INFO_SET_IOVA 0x04 69 #define MSM_INFO_GET_FLAGS 0x05 70 #define MSM_INFO_SET_METADATA 0x06 71 #define MSM_INFO_GET_METADATA 0x07 72 struct drm_msm_gem_info { 73 __u32 handle; 74 __u32 info; 75 __u64 value; 76 __u32 len; 77 __u32 pad; 78 }; 79 #define MSM_PREP_READ 0x01 80 #define MSM_PREP_WRITE 0x02 81 #define MSM_PREP_NOSYNC 0x04 82 #define MSM_PREP_BOOST 0x08 83 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC | MSM_PREP_BOOST | 0) 84 struct drm_msm_gem_cpu_prep { 85 __u32 handle; 86 __u32 op; 87 struct drm_msm_timespec timeout; 88 }; 89 struct drm_msm_gem_cpu_fini { 90 __u32 handle; 91 }; 92 struct drm_msm_gem_submit_reloc { 93 __u32 submit_offset; 94 #ifdef __cplusplus 95 __u32 _or; 96 #else 97 __u32 or; 98 #endif 99 __s32 shift; 100 __u32 reloc_idx; 101 __u64 reloc_offset; 102 }; 103 #define MSM_SUBMIT_CMD_BUF 0x0001 104 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 105 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 106 struct drm_msm_gem_submit_cmd { 107 __u32 type; 108 __u32 submit_idx; 109 __u32 submit_offset; 110 __u32 size; 111 __u32 pad; 112 __u32 nr_relocs; 113 __u64 relocs; 114 }; 115 #define MSM_SUBMIT_BO_READ 0x0001 116 #define MSM_SUBMIT_BO_WRITE 0x0002 117 #define MSM_SUBMIT_BO_DUMP 0x0004 118 #define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008 119 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP | MSM_SUBMIT_BO_NO_IMPLICIT) 120 struct drm_msm_gem_submit_bo { 121 __u32 flags; 122 __u32 handle; 123 __u64 presumed; 124 }; 125 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 126 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 127 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 128 #define MSM_SUBMIT_SUDO 0x10000000 129 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 130 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 131 #define MSM_SUBMIT_FENCE_SN_IN 0x02000000 132 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | MSM_SUBMIT_FENCE_SN_IN | 0) 133 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 134 #define MSM_SUBMIT_SYNCOBJ_FLAGS (MSM_SUBMIT_SYNCOBJ_RESET | 0) 135 struct drm_msm_gem_submit_syncobj { 136 __u32 handle; 137 __u32 flags; 138 __u64 point; 139 }; 140 struct drm_msm_gem_submit { 141 __u32 flags; 142 __u32 fence; 143 __u32 nr_bos; 144 __u32 nr_cmds; 145 __u64 bos; 146 __u64 cmds; 147 __s32 fence_fd; 148 __u32 queueid; 149 __u64 in_syncobjs; 150 __u64 out_syncobjs; 151 __u32 nr_in_syncobjs; 152 __u32 nr_out_syncobjs; 153 __u32 syncobj_stride; 154 __u32 pad; 155 }; 156 #define MSM_WAIT_FENCE_BOOST 0x00000001 157 #define MSM_WAIT_FENCE_FLAGS (MSM_WAIT_FENCE_BOOST | 0) 158 struct drm_msm_wait_fence { 159 __u32 fence; 160 __u32 flags; 161 struct drm_msm_timespec timeout; 162 __u32 queueid; 163 }; 164 #define MSM_MADV_WILLNEED 0 165 #define MSM_MADV_DONTNEED 1 166 #define __MSM_MADV_PURGED 2 167 struct drm_msm_gem_madvise { 168 __u32 handle; 169 __u32 madv; 170 __u32 retained; 171 }; 172 #define MSM_SUBMITQUEUE_FLAGS (0) 173 struct drm_msm_submitqueue { 174 __u32 flags; 175 __u32 prio; 176 __u32 id; 177 }; 178 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 179 struct drm_msm_submitqueue_query { 180 __u64 data; 181 __u32 id; 182 __u32 param; 183 __u32 len; 184 __u32 pad; 185 }; 186 #define DRM_MSM_GET_PARAM 0x00 187 #define DRM_MSM_SET_PARAM 0x01 188 #define DRM_MSM_GEM_NEW 0x02 189 #define DRM_MSM_GEM_INFO 0x03 190 #define DRM_MSM_GEM_CPU_PREP 0x04 191 #define DRM_MSM_GEM_CPU_FINI 0x05 192 #define DRM_MSM_GEM_SUBMIT 0x06 193 #define DRM_MSM_WAIT_FENCE 0x07 194 #define DRM_MSM_GEM_MADVISE 0x08 195 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 196 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 197 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 198 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 199 #define DRM_IOCTL_MSM_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) 200 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 201 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 202 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 203 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 204 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 205 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 206 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 207 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 208 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 209 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 210 #ifdef __cplusplus 211 } 212 #endif 213 #endif 214