1// Copyright 2016 The Go Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style 3// license that can be found in the LICENSE file. 4 5// Lowering arithmetic 6(Add(Ptr|32|16|8) ...) => (ADDL ...) 7(Add(32|64)F ...) => (ADDS(S|D) ...) 8(Add32carry ...) => (ADDLcarry ...) 9(Add32withcarry ...) => (ADCL ...) 10 11(Sub(Ptr|32|16|8) ...) => (SUBL ...) 12(Sub(32|64)F ...) => (SUBS(S|D) ...) 13(Sub32carry ...) => (SUBLcarry ...) 14(Sub32withcarry ...) => (SBBL ...) 15 16(Mul(32|16|8) ...) => (MULL ...) 17(Mul(32|64)F ...) => (MULS(S|D) ...) 18(Mul32uhilo ...) => (MULLQU ...) 19 20(Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y)) 21(Select1 (Mul32uover x y)) => (SETO (Select1 <types.TypeFlags> (MULLU x y))) 22 23(Avg32u ...) => (AVGLU ...) 24 25(Div(32|64)F ...) => (DIVS(S|D) ...) 26(Div(32|32u|16|16u) ...) => (DIV(L|LU|W|WU) ...) 27(Div8 x y) => (DIVW (SignExt8to16 x) (SignExt8to16 y)) 28(Div8u x y) => (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)) 29 30(Hmul(32|32u) ...) => (HMUL(L|LU) ...) 31 32(Mod(32|32u|16|16u) ...) => (MOD(L|LU|W|WU) ...) 33(Mod8 x y) => (MODW (SignExt8to16 x) (SignExt8to16 y)) 34(Mod8u x y) => (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y)) 35 36(And(32|16|8) ...) => (ANDL ...) 37(Or(32|16|8) ...) => (ORL ...) 38(Xor(32|16|8) ...) => (XORL ...) 39 40(Neg(32|16|8) ...) => (NEGL ...) 41(Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))])) 42(Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)])) 43 44(Com(32|16|8) ...) => (NOTL ...) 45 46// Lowering boolean ops 47(AndB ...) => (ANDL ...) 48(OrB ...) => (ORL ...) 49(Not x) => (XORLconst [1] x) 50 51// Lowering pointer arithmetic 52(OffPtr [off] ptr) => (ADDLconst [int32(off)] ptr) 53 54(Bswap32 ...) => (BSWAPL ...) 55(Bswap16 x) => (ROLWconst [8] x) 56 57(Sqrt ...) => (SQRTSD ...) 58(Sqrt32 ...) => (SQRTSS ...) 59 60(Ctz8 x) => (BSFL (ORLconst <typ.UInt32> [0x100] x)) 61(Ctz8NonZero ...) => (BSFL ...) 62(Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [0x10000] x)) 63(Ctz16NonZero ...) => (BSFL ...) 64(Ctz32 ...) => (LoweredCtz32 ...) 65(Ctz32NonZero ...) => (BSFL ...) 66 67// Lowering extension 68(SignExt8to16 ...) => (MOVBLSX ...) 69(SignExt8to32 ...) => (MOVBLSX ...) 70(SignExt16to32 ...) => (MOVWLSX ...) 71 72(ZeroExt8to16 ...) => (MOVBLZX ...) 73(ZeroExt8to32 ...) => (MOVBLZX ...) 74(ZeroExt16to32 ...) => (MOVWLZX ...) 75 76(Signmask x) => (SARLconst x [31]) 77(Zeromask <t> x) => (XORLconst [-1] (SBBLcarrymask <t> (CMPLconst x [1]))) 78(Slicemask <t> x) => (SARLconst (NEGL <t> x) [31]) 79 80// Lowering truncation 81// Because we ignore high parts of registers, truncates are just copies. 82(Trunc16to8 ...) => (Copy ...) 83(Trunc32to8 ...) => (Copy ...) 84(Trunc32to16 ...) => (Copy ...) 85 86// Lowering float-int conversions 87(Cvt32to32F ...) => (CVTSL2SS ...) 88(Cvt32to64F ...) => (CVTSL2SD ...) 89 90(Cvt32Fto32 ...) => (CVTTSS2SL ...) 91(Cvt64Fto32 ...) => (CVTTSD2SL ...) 92 93(Cvt32Fto64F ...) => (CVTSS2SD ...) 94(Cvt64Fto32F ...) => (CVTSD2SS ...) 95 96(Round32F ...) => (Copy ...) 97(Round64F ...) => (Copy ...) 98 99(CvtBoolToUint8 ...) => (Copy ...) 100 101// Lowering shifts 102// Unsigned shifts need to return 0 if shift amount is >= width of shifted value. 103// result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) 104(Lsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32]))) 105(Lsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32]))) 106(Lsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32]))) 107 108(Lsh32x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y) 109(Lsh16x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y) 110(Lsh8x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y) 111 112(Rsh32Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32]))) 113(Rsh16Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [16]))) 114(Rsh8Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [8]))) 115 116(Rsh32Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRL <t> x y) 117(Rsh16Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRW <t> x y) 118(Rsh8Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRB <t> x y) 119 120// Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. 121// We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. 122 123(Rsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [32]))))) 124(Rsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [16]))))) 125(Rsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [8]))))) 126 127(Rsh32x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARL x y) 128(Rsh16x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARW x y) 129(Rsh8x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARB x y) 130 131// constant shifts 132// generic opt rewrites all constant shifts to shift by Const64 133(Lsh32x64 x (Const64 [c])) && uint64(c) < 32 => (SHLLconst x [int32(c)]) 134(Rsh32x64 x (Const64 [c])) && uint64(c) < 32 => (SARLconst x [int32(c)]) 135(Rsh32Ux64 x (Const64 [c])) && uint64(c) < 32 => (SHRLconst x [int32(c)]) 136(Lsh16x64 x (Const64 [c])) && uint64(c) < 16 => (SHLLconst x [int32(c)]) 137(Rsh16x64 x (Const64 [c])) && uint64(c) < 16 => (SARWconst x [int16(c)]) 138(Rsh16Ux64 x (Const64 [c])) && uint64(c) < 16 => (SHRWconst x [int16(c)]) 139(Lsh8x64 x (Const64 [c])) && uint64(c) < 8 => (SHLLconst x [int32(c)]) 140(Rsh8x64 x (Const64 [c])) && uint64(c) < 8 => (SARBconst x [int8(c)]) 141(Rsh8Ux64 x (Const64 [c])) && uint64(c) < 8 => (SHRBconst x [int8(c)]) 142 143// large constant shifts 144(Lsh32x64 _ (Const64 [c])) && uint64(c) >= 32 => (Const32 [0]) 145(Rsh32Ux64 _ (Const64 [c])) && uint64(c) >= 32 => (Const32 [0]) 146(Lsh16x64 _ (Const64 [c])) && uint64(c) >= 16 => (Const16 [0]) 147(Rsh16Ux64 _ (Const64 [c])) && uint64(c) >= 16 => (Const16 [0]) 148(Lsh8x64 _ (Const64 [c])) && uint64(c) >= 8 => (Const8 [0]) 149(Rsh8Ux64 _ (Const64 [c])) && uint64(c) >= 8 => (Const8 [0]) 150 151// large constant signed right shift, we leave the sign bit 152(Rsh32x64 x (Const64 [c])) && uint64(c) >= 32 => (SARLconst x [31]) 153(Rsh16x64 x (Const64 [c])) && uint64(c) >= 16 => (SARWconst x [15]) 154(Rsh8x64 x (Const64 [c])) && uint64(c) >= 8 => (SARBconst x [7]) 155 156// rotates 157(RotateLeft32 ...) => (ROLL ...) 158(RotateLeft16 ...) => (ROLW ...) 159(RotateLeft8 ...) => (ROLB ...) 160// constant rotates 161(ROLL x (MOVLconst [c])) => (ROLLconst [c&31] x) 162(ROLW x (MOVLconst [c])) => (ROLWconst [int16(c&15)] x) 163(ROLB x (MOVLconst [c])) => (ROLBconst [int8(c&7)] x) 164 165// Lowering comparisons 166(Less32 x y) => (SETL (CMPL x y)) 167(Less16 x y) => (SETL (CMPW x y)) 168(Less8 x y) => (SETL (CMPB x y)) 169(Less32U x y) => (SETB (CMPL x y)) 170(Less16U x y) => (SETB (CMPW x y)) 171(Less8U x y) => (SETB (CMPB x y)) 172// Use SETGF with reversed operands to dodge NaN case 173(Less64F x y) => (SETGF (UCOMISD y x)) 174(Less32F x y) => (SETGF (UCOMISS y x)) 175 176(Leq32 x y) => (SETLE (CMPL x y)) 177(Leq16 x y) => (SETLE (CMPW x y)) 178(Leq8 x y) => (SETLE (CMPB x y)) 179(Leq32U x y) => (SETBE (CMPL x y)) 180(Leq16U x y) => (SETBE (CMPW x y)) 181(Leq8U x y) => (SETBE (CMPB x y)) 182// Use SETGEF with reversed operands to dodge NaN case 183(Leq64F x y) => (SETGEF (UCOMISD y x)) 184(Leq32F x y) => (SETGEF (UCOMISS y x)) 185 186(Eq32 x y) => (SETEQ (CMPL x y)) 187(Eq16 x y) => (SETEQ (CMPW x y)) 188(Eq8 x y) => (SETEQ (CMPB x y)) 189(EqB x y) => (SETEQ (CMPB x y)) 190(EqPtr x y) => (SETEQ (CMPL x y)) 191(Eq64F x y) => (SETEQF (UCOMISD x y)) 192(Eq32F x y) => (SETEQF (UCOMISS x y)) 193 194(Neq32 x y) => (SETNE (CMPL x y)) 195(Neq16 x y) => (SETNE (CMPW x y)) 196(Neq8 x y) => (SETNE (CMPB x y)) 197(NeqB x y) => (SETNE (CMPB x y)) 198(NeqPtr x y) => (SETNE (CMPL x y)) 199(Neq64F x y) => (SETNEF (UCOMISD x y)) 200(Neq32F x y) => (SETNEF (UCOMISS x y)) 201 202// Lowering loads 203(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVLload ptr mem) 204(Load <t> ptr mem) && is16BitInt(t) => (MOVWload ptr mem) 205(Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) => (MOVBload ptr mem) 206(Load <t> ptr mem) && is32BitFloat(t) => (MOVSSload ptr mem) 207(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem) 208 209// Lowering stores 210(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem) 211(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem) 212(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem) 213(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem) 214(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem) 215 216// Lowering moves 217(Move [0] _ _ mem) => mem 218(Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem) 219(Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem) 220(Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem) 221(Move [3] dst src mem) => 222 (MOVBstore [2] dst (MOVBload [2] src mem) 223 (MOVWstore dst (MOVWload src mem) mem)) 224(Move [5] dst src mem) => 225 (MOVBstore [4] dst (MOVBload [4] src mem) 226 (MOVLstore dst (MOVLload src mem) mem)) 227(Move [6] dst src mem) => 228 (MOVWstore [4] dst (MOVWload [4] src mem) 229 (MOVLstore dst (MOVLload src mem) mem)) 230(Move [7] dst src mem) => 231 (MOVLstore [3] dst (MOVLload [3] src mem) 232 (MOVLstore dst (MOVLload src mem) mem)) 233(Move [8] dst src mem) => 234 (MOVLstore [4] dst (MOVLload [4] src mem) 235 (MOVLstore dst (MOVLload src mem) mem)) 236 237// Adjust moves to be a multiple of 4 bytes. 238(Move [s] dst src mem) 239 && s > 8 && s%4 != 0 => 240 (Move [s-s%4] 241 (ADDLconst <dst.Type> dst [int32(s%4)]) 242 (ADDLconst <src.Type> src [int32(s%4)]) 243 (MOVLstore dst (MOVLload src mem) mem)) 244 245// Medium copying uses a duff device. 246(Move [s] dst src mem) 247 && s > 8 && s <= 4*128 && s%4 == 0 248 && !config.noDuffDevice && logLargeCopy(v, s) => 249 (DUFFCOPY [10*(128-s/4)] dst src mem) 250// 10 and 128 are magic constants. 10 is the number of bytes to encode: 251// MOVL (SI), CX 252// ADDL $4, SI 253// MOVL CX, (DI) 254// ADDL $4, DI 255// and 128 is the number of such blocks. See src/runtime/duff_386.s:duffcopy. 256 257// Large copying uses REP MOVSL. 258(Move [s] dst src mem) && (s > 4*128 || config.noDuffDevice) && s%4 == 0 && logLargeCopy(v, s) => 259 (REPMOVSL dst src (MOVLconst [int32(s/4)]) mem) 260 261// Lowering Zero instructions 262(Zero [0] _ mem) => mem 263(Zero [1] destptr mem) => (MOVBstoreconst [0] destptr mem) 264(Zero [2] destptr mem) => (MOVWstoreconst [0] destptr mem) 265(Zero [4] destptr mem) => (MOVLstoreconst [0] destptr mem) 266 267(Zero [3] destptr mem) => 268 (MOVBstoreconst [makeValAndOff(0,2)] destptr 269 (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)) 270(Zero [5] destptr mem) => 271 (MOVBstoreconst [makeValAndOff(0,4)] destptr 272 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) 273(Zero [6] destptr mem) => 274 (MOVWstoreconst [makeValAndOff(0,4)] destptr 275 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) 276(Zero [7] destptr mem) => 277 (MOVLstoreconst [makeValAndOff(0,3)] destptr 278 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) 279 280// Strip off any fractional word zeroing. 281(Zero [s] destptr mem) && s%4 != 0 && s > 4 => 282 (Zero [s-s%4] (ADDLconst destptr [int32(s%4)]) 283 (MOVLstoreconst [0] destptr mem)) 284 285// Zero small numbers of words directly. 286(Zero [8] destptr mem) => 287 (MOVLstoreconst [makeValAndOff(0,4)] destptr 288 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)) 289(Zero [12] destptr mem) => 290 (MOVLstoreconst [makeValAndOff(0,8)] destptr 291 (MOVLstoreconst [makeValAndOff(0,4)] destptr 292 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))) 293(Zero [16] destptr mem) => 294 (MOVLstoreconst [makeValAndOff(0,12)] destptr 295 (MOVLstoreconst [makeValAndOff(0,8)] destptr 296 (MOVLstoreconst [makeValAndOff(0,4)] destptr 297 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)))) 298 299// Medium zeroing uses a duff device. 300(Zero [s] destptr mem) 301 && s > 16 && s <= 4*128 && s%4 == 0 302 && !config.noDuffDevice => 303 (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem) 304// 1 and 128 are magic constants. 1 is the number of bytes to encode STOSL. 305// 128 is the number of STOSL instructions in duffzero. 306// See src/runtime/duff_386.s:duffzero. 307 308// Large zeroing uses REP STOSQ. 309(Zero [s] destptr mem) 310 && (s > 4*128 || (config.noDuffDevice && s > 16)) 311 && s%4 == 0 => 312 (REPSTOSL destptr (MOVLconst [int32(s/4)]) (MOVLconst [0]) mem) 313 314 315// Lowering constants 316(Const8 [c]) => (MOVLconst [int32(c)]) 317(Const16 [c]) => (MOVLconst [int32(c)]) 318(Const32 ...) => (MOVLconst ...) 319(Const(32|64)F ...) => (MOVS(S|D)const ...) 320(ConstNil) => (MOVLconst [0]) 321(ConstBool [c]) => (MOVLconst [b2i32(c)]) 322 323// Lowering calls 324(StaticCall ...) => (CALLstatic ...) 325(ClosureCall ...) => (CALLclosure ...) 326(InterCall ...) => (CALLinter ...) 327(TailCall ...) => (CALLtail ...) 328 329// Miscellaneous 330(IsNonNil p) => (SETNE (TESTL p p)) 331(IsInBounds idx len) => (SETB (CMPL idx len)) 332(IsSliceInBounds idx len) => (SETBE (CMPL idx len)) 333(NilCheck ...) => (LoweredNilCheck ...) 334(GetG ...) => (LoweredGetG ...) 335(GetClosurePtr ...) => (LoweredGetClosurePtr ...) 336(GetCallerPC ...) => (LoweredGetCallerPC ...) 337(GetCallerSP ...) => (LoweredGetCallerSP ...) 338(Addr {sym} base) => (LEAL {sym} base) 339(LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (LEAL {sym} (SPanchored base mem)) 340(LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (LEAL {sym} base) 341 342// block rewrites 343(If (SETL cmp) yes no) => (LT cmp yes no) 344(If (SETLE cmp) yes no) => (LE cmp yes no) 345(If (SETG cmp) yes no) => (GT cmp yes no) 346(If (SETGE cmp) yes no) => (GE cmp yes no) 347(If (SETEQ cmp) yes no) => (EQ cmp yes no) 348(If (SETNE cmp) yes no) => (NE cmp yes no) 349(If (SETB cmp) yes no) => (ULT cmp yes no) 350(If (SETBE cmp) yes no) => (ULE cmp yes no) 351(If (SETA cmp) yes no) => (UGT cmp yes no) 352(If (SETAE cmp) yes no) => (UGE cmp yes no) 353(If (SETO cmp) yes no) => (OS cmp yes no) 354 355// Special case for floating point - LF/LEF not generated 356(If (SETGF cmp) yes no) => (UGT cmp yes no) 357(If (SETGEF cmp) yes no) => (UGE cmp yes no) 358(If (SETEQF cmp) yes no) => (EQF cmp yes no) 359(If (SETNEF cmp) yes no) => (NEF cmp yes no) 360 361(If cond yes no) => (NE (TESTB cond cond) yes no) 362 363// Write barrier. 364(WB ...) => (LoweredWB ...) 365 366(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem) 367(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem) 368(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem) 369 370(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 => (LoweredPanicExtendA [kind] hi lo y mem) 371(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 => (LoweredPanicExtendB [kind] hi lo y mem) 372(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem) 373 374// *************************** 375// Above: lowering rules 376// Below: optimizations 377// *************************** 378// TODO: Should the optimizations be a separate pass? 379 380// Fold boolean tests into blocks 381(NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no) 382(NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no) 383(NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no) 384(NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no) 385(NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no) 386(NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no) 387(NE (TESTB (SETB cmp) (SETB cmp)) yes no) => (ULT cmp yes no) 388(NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no) 389(NE (TESTB (SETA cmp) (SETA cmp)) yes no) => (UGT cmp yes no) 390(NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no) 391(NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no) 392 393// Special case for floating point - LF/LEF not generated 394(NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) => (UGT cmp yes no) 395(NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE cmp yes no) 396(NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF cmp yes no) 397(NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF cmp yes no) 398 399// fold constants into instructions 400(ADDL x (MOVLconst <t> [c])) && !t.IsPtr() => (ADDLconst [c] x) 401(ADDLcarry x (MOVLconst [c])) => (ADDLconstcarry [c] x) 402(ADCL x (MOVLconst [c]) f) => (ADCLconst [c] x f) 403 404(SUBL x (MOVLconst [c])) => (SUBLconst x [c]) 405(SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c])) 406(SUBLcarry x (MOVLconst [c])) => (SUBLconstcarry [c] x) 407(SBBL x (MOVLconst [c]) f) => (SBBLconst [c] x f) 408 409(MULL x (MOVLconst [c])) => (MULLconst [c] x) 410(ANDL x (MOVLconst [c])) => (ANDLconst [c] x) 411 412(ANDLconst [c] (ANDLconst [d] x)) => (ANDLconst [c & d] x) 413(XORLconst [c] (XORLconst [d] x)) => (XORLconst [c ^ d] x) 414(MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x) 415 416(ORL x (MOVLconst [c])) => (ORLconst [c] x) 417(XORL x (MOVLconst [c])) => (XORLconst [c] x) 418 419(SHLL x (MOVLconst [c])) => (SHLLconst [c&31] x) 420(SHRL x (MOVLconst [c])) => (SHRLconst [c&31] x) 421(SHRW x (MOVLconst [c])) && c&31 < 16 => (SHRWconst [int16(c&31)] x) 422(SHRW _ (MOVLconst [c])) && c&31 >= 16 => (MOVLconst [0]) 423(SHRB x (MOVLconst [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x) 424(SHRB _ (MOVLconst [c])) && c&31 >= 8 => (MOVLconst [0]) 425 426(SARL x (MOVLconst [c])) => (SARLconst [c&31] x) 427(SARW x (MOVLconst [c])) => (SARWconst [int16(min(int64(c&31),15))] x) 428(SARB x (MOVLconst [c])) => (SARBconst [int8(min(int64(c&31),7))] x) 429 430(SARL x (ANDLconst [31] y)) => (SARL x y) 431(SHLL x (ANDLconst [31] y)) => (SHLL x y) 432(SHRL x (ANDLconst [31] y)) => (SHRL x y) 433 434// Constant shift simplifications 435 436(SHLLconst x [0]) => x 437(SHRLconst x [0]) => x 438(SARLconst x [0]) => x 439 440(SHRWconst x [0]) => x 441(SARWconst x [0]) => x 442 443(SHRBconst x [0]) => x 444(SARBconst x [0]) => x 445 446(ROLLconst [0] x) => x 447(ROLWconst [0] x) => x 448(ROLBconst [0] x) => x 449 450// Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits) 451// because the x86 instructions are defined to use all 5 bits of the shift even 452// for the small shifts. I don't think we'll ever generate a weird shift (e.g. 453// (SHRW x (MOVLconst [24])), but just in case. 454 455(CMPL x (MOVLconst [c])) => (CMPLconst x [c]) 456(CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c])) 457(CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)]) 458(CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)])) 459(CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)]) 460(CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)])) 461 462// Canonicalize the order of arguments to comparisons - helps with CSE. 463(CMP(L|W|B) x y) && canonLessThan(x,y) => (InvertFlags (CMP(L|W|B) y x)) 464 465// strength reduction 466// Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf: 467// 1 - addl, shll, leal, negl, subl 468// 3 - imull 469// This limits the rewrites to two instructions. 470// Note that negl always operates in-place, 471// which can require a register-register move 472// to preserve the original value, 473// so it must be used with care. 474(MULLconst [-9] x) => (NEGL (LEAL8 <v.Type> x x)) 475(MULLconst [-5] x) => (NEGL (LEAL4 <v.Type> x x)) 476(MULLconst [-3] x) => (NEGL (LEAL2 <v.Type> x x)) 477(MULLconst [-1] x) => (NEGL x) 478(MULLconst [0] _) => (MOVLconst [0]) 479(MULLconst [1] x) => x 480(MULLconst [3] x) => (LEAL2 x x) 481(MULLconst [5] x) => (LEAL4 x x) 482(MULLconst [7] x) => (LEAL2 x (LEAL2 <v.Type> x x)) 483(MULLconst [9] x) => (LEAL8 x x) 484(MULLconst [11] x) => (LEAL2 x (LEAL4 <v.Type> x x)) 485(MULLconst [13] x) => (LEAL4 x (LEAL2 <v.Type> x x)) 486(MULLconst [19] x) => (LEAL2 x (LEAL8 <v.Type> x x)) 487(MULLconst [21] x) => (LEAL4 x (LEAL4 <v.Type> x x)) 488(MULLconst [25] x) => (LEAL8 x (LEAL2 <v.Type> x x)) 489(MULLconst [27] x) => (LEAL8 (LEAL2 <v.Type> x x) (LEAL2 <v.Type> x x)) 490(MULLconst [37] x) => (LEAL4 x (LEAL8 <v.Type> x x)) 491(MULLconst [41] x) => (LEAL8 x (LEAL4 <v.Type> x x)) 492(MULLconst [45] x) => (LEAL8 (LEAL4 <v.Type> x x) (LEAL4 <v.Type> x x)) 493(MULLconst [73] x) => (LEAL8 x (LEAL8 <v.Type> x x)) 494(MULLconst [81] x) => (LEAL8 (LEAL8 <v.Type> x x) (LEAL8 <v.Type> x x)) 495 496(MULLconst [c] x) && isPowerOfTwo32(c+1) && c >= 15 => (SUBL (SHLLconst <v.Type> [int32(log32(c+1))] x) x) 497(MULLconst [c] x) && isPowerOfTwo32(c-1) && c >= 17 => (LEAL1 (SHLLconst <v.Type> [int32(log32(c-1))] x) x) 498(MULLconst [c] x) && isPowerOfTwo32(c-2) && c >= 34 => (LEAL2 (SHLLconst <v.Type> [int32(log32(c-2))] x) x) 499(MULLconst [c] x) && isPowerOfTwo32(c-4) && c >= 68 => (LEAL4 (SHLLconst <v.Type> [int32(log32(c-4))] x) x) 500(MULLconst [c] x) && isPowerOfTwo32(c-8) && c >= 136 => (LEAL8 (SHLLconst <v.Type> [int32(log32(c-8))] x) x) 501(MULLconst [c] x) && c%3 == 0 && isPowerOfTwo32(c/3) => (SHLLconst [int32(log32(c/3))] (LEAL2 <v.Type> x x)) 502(MULLconst [c] x) && c%5 == 0 && isPowerOfTwo32(c/5) => (SHLLconst [int32(log32(c/5))] (LEAL4 <v.Type> x x)) 503(MULLconst [c] x) && c%9 == 0 && isPowerOfTwo32(c/9) => (SHLLconst [int32(log32(c/9))] (LEAL8 <v.Type> x x)) 504 505// combine add/shift into LEAL 506(ADDL x (SHLLconst [3] y)) => (LEAL8 x y) 507(ADDL x (SHLLconst [2] y)) => (LEAL4 x y) 508(ADDL x (SHLLconst [1] y)) => (LEAL2 x y) 509(ADDL x (ADDL y y)) => (LEAL2 x y) 510(ADDL x (ADDL x y)) => (LEAL2 y x) 511 512// combine ADDL/ADDLconst into LEAL1 513(ADDLconst [c] (ADDL x y)) => (LEAL1 [c] x y) 514(ADDL (ADDLconst [c] x) y) => (LEAL1 [c] x y) 515 516// fold ADDL into LEAL 517(ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(int64(c)+int64(d)) => (LEAL [c+d] {s} x) 518(LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(int64(c)+int64(d)) => (LEAL [c+d] {s} x) 519(ADDLconst [c] x:(SP)) => (LEAL [c] x) // so it is rematerializeable 520(LEAL [c] {s} (ADDL x y)) && x.Op != OpSB && y.Op != OpSB => (LEAL1 [c] {s} x y) 521(ADDL x (LEAL [c] {s} y)) && x.Op != OpSB && y.Op != OpSB => (LEAL1 [c] {s} x y) 522 523// fold ADDLconst into LEALx 524(ADDLconst [c] (LEAL1 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL1 [c+d] {s} x y) 525(ADDLconst [c] (LEAL2 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL2 [c+d] {s} x y) 526(ADDLconst [c] (LEAL4 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL4 [c+d] {s} x y) 527(ADDLconst [c] (LEAL8 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL8 [c+d] {s} x y) 528(LEAL1 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL1 [c+d] {s} x y) 529(LEAL2 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL2 [c+d] {s} x y) 530(LEAL2 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB => (LEAL2 [c+2*d] {s} x y) 531(LEAL4 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL4 [c+d] {s} x y) 532(LEAL4 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB => (LEAL4 [c+4*d] {s} x y) 533(LEAL8 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL8 [c+d] {s} x y) 534(LEAL8 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB => (LEAL8 [c+8*d] {s} x y) 535 536// fold shifts into LEALx 537(LEAL1 [c] {s} x (SHLLconst [1] y)) => (LEAL2 [c] {s} x y) 538(LEAL1 [c] {s} x (SHLLconst [2] y)) => (LEAL4 [c] {s} x y) 539(LEAL1 [c] {s} x (SHLLconst [3] y)) => (LEAL8 [c] {s} x y) 540(LEAL2 [c] {s} x (SHLLconst [1] y)) => (LEAL4 [c] {s} x y) 541(LEAL2 [c] {s} x (SHLLconst [2] y)) => (LEAL8 [c] {s} x y) 542(LEAL4 [c] {s} x (SHLLconst [1] y)) => (LEAL8 [c] {s} x y) 543 544// reverse ordering of compare instruction 545(SETL (InvertFlags x)) => (SETG x) 546(SETG (InvertFlags x)) => (SETL x) 547(SETB (InvertFlags x)) => (SETA x) 548(SETA (InvertFlags x)) => (SETB x) 549(SETLE (InvertFlags x)) => (SETGE x) 550(SETGE (InvertFlags x)) => (SETLE x) 551(SETBE (InvertFlags x)) => (SETAE x) 552(SETAE (InvertFlags x)) => (SETBE x) 553(SETEQ (InvertFlags x)) => (SETEQ x) 554(SETNE (InvertFlags x)) => (SETNE x) 555 556// sign extended loads 557// Note: The combined instruction must end up in the same block 558// as the original load. If not, we end up making a value with 559// memory type live in two different blocks, which can lead to 560// multiple memory values alive simultaneously. 561// Make sure we don't combine these ops if the load has another use. 562// This prevents a single load from being split into multiple loads 563// which then might return different values. See test/atomicload.go. 564(MOVBLSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBLSXload <v.Type> [off] {sym} ptr mem) 565(MOVBLZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 566(MOVWLSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWLSXload <v.Type> [off] {sym} ptr mem) 567(MOVWLZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 568 569// replace load from same location as preceding store with zero/sign extension (or copy in case of full width) 570(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBLZX x) 571(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWLZX x) 572(MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x 573(MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBLSX x) 574(MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWLSX x) 575 576// Fold extensions and ANDs together. 577(MOVBLZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x) 578(MOVWLZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x) 579(MOVBLSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x) 580(MOVWLSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x) 581 582// Don't extend before storing 583(MOVWstore [off] {sym} ptr (MOVWL(S|Z)X x) mem) => (MOVWstore [off] {sym} ptr x mem) 584(MOVBstore [off] {sym} ptr (MOVBL(S|Z)X x) mem) => (MOVBstore [off] {sym} ptr x mem) 585 586// fold constants into memory operations 587// Note that this is not always a good idea because if not all the uses of 588// the ADDLconst get eliminated, we still have to compute the ADDLconst and we now 589// have potentially two live values (ptr and (ADDLconst [off] ptr)) instead of one. 590// Nevertheless, let's do it! 591(MOV(L|W|B|SS|SD)load [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) => 592 (MOV(L|W|B|SS|SD)load [off1+off2] {sym} ptr mem) 593(MOV(L|W|B|SS|SD)store [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) => 594 (MOV(L|W|B|SS|SD)store [off1+off2] {sym} ptr val mem) 595 596((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) => 597 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {sym} val base mem) 598((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) => 599 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem) 600((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) => 601 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem) 602((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDLconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) => 603 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem) 604((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) && valoff1.canAdd32(off2) => 605 ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {sym} base mem) 606 607// Fold constants into stores. 608(MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) => 609 (MOVLstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 610(MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) => 611 (MOVWstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 612(MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) => 613 (MOVBstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 614 615// Fold address offsets into constant stores. 616(MOV(L|W|B)storeconst [sc] {s} (ADDLconst [off] ptr) mem) && sc.canAdd32(off) => 617 (MOV(L|W|B)storeconst [sc.addOffset32(off)] {s} ptr mem) 618 619// We need to fold LEAL into the MOVx ops so that the live variable analysis knows 620// what variables are being read/written by the ops. 621// Note: we turn off this merging for operations on globals when building 622// position-independent code (when Flag_shared is set). 623// PIC needs a spare register to load the PC into. Having the LEAL be 624// a separate instruction gives us that register. Having the LEAL be 625// a separate instruction also allows it to be CSEd (which is good because 626// it compiles to a thunk call). 627(MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) 628 && (base.Op != OpSB || !config.ctxt.Flag_shared) => 629 (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem) 630 631(MOV(L|W|B|SS|SD)store [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) 632 && (base.Op != OpSB || !config.ctxt.Flag_shared) => 633 (MOV(L|W|B|SS|SD)store [off1+off2] {mergeSym(sym1,sym2)} base val mem) 634 635(MOV(L|W|B)storeconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off) 636 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => 637 (MOV(L|W|B)storeconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem) 638 639((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) 640 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => 641 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem) 642((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) 643 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => 644 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem) 645((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem) 646 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => 647 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem) 648((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem) 649 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => 650 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem) 651((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem) 652 && valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) => 653 ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem) 654 655// Merge load/store to op 656((ADD|AND|OR|XOR|SUB|MUL)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|AND|OR|XOR|SUB|MUL)Lload x [off] {sym} ptr mem) 657((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem) 658((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem) 659(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem) 660(MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) => 661 ((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem) 662(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr mem)) mem) 663 && y.Uses==1 && l.Uses==1 && clobber(y, l) => 664 ((ADD|AND|OR|XOR)Lconstmodify [makeValAndOff(c,off)] {sym} ptr mem) 665 666// fold LEALs together 667(LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 668 (LEAL [off1+off2] {mergeSym(sym1,sym2)} x) 669 670// LEAL into LEAL1 671(LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => 672 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) 673 674// LEAL1 into LEAL 675(LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 676 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y) 677 678// LEAL into LEAL[248] 679(LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => 680 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) 681(LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => 682 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) 683(LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB => 684 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) 685 686// LEAL[248] into LEAL 687(LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 688 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y) 689(LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 690 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y) 691(LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 692 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y) 693 694// LEAL[1248] into LEAL[1248]. Only some such merges are possible. 695(LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 696 (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} x y) 697(LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) => 698 (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} y x) 699(LEAL2 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+2*int64(off2)) => 700 (LEAL4 [off1+2*off2] {sym} x y) 701(LEAL4 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+4*int64(off2)) => 702 (LEAL8 [off1+4*off2] {sym} x y) 703 704// Absorb InvertFlags into branches. 705(LT (InvertFlags cmp) yes no) => (GT cmp yes no) 706(GT (InvertFlags cmp) yes no) => (LT cmp yes no) 707(LE (InvertFlags cmp) yes no) => (GE cmp yes no) 708(GE (InvertFlags cmp) yes no) => (LE cmp yes no) 709(ULT (InvertFlags cmp) yes no) => (UGT cmp yes no) 710(UGT (InvertFlags cmp) yes no) => (ULT cmp yes no) 711(ULE (InvertFlags cmp) yes no) => (UGE cmp yes no) 712(UGE (InvertFlags cmp) yes no) => (ULE cmp yes no) 713(EQ (InvertFlags cmp) yes no) => (EQ cmp yes no) 714(NE (InvertFlags cmp) yes no) => (NE cmp yes no) 715 716// Constant comparisons. 717(CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ) 718(CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT) 719(CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT) 720(CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT) 721(CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT) 722 723(CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ) 724(CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT) 725(CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT) 726(CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT) 727(CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT) 728 729(CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ) 730(CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT) 731(CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT) 732(CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT) 733(CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT) 734 735// Other known comparisons. 736(CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT) 737(CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT) 738(CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT) 739(CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < n => (FlagLT_ULT) 740// TODO: DIVxU also. 741 742// Absorb flag constants into SBB ops. 743(SBBLcarrymask (FlagEQ)) => (MOVLconst [0]) 744(SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1]) 745(SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0]) 746(SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1]) 747(SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0]) 748 749// Absorb flag constants into branches. 750(EQ (FlagEQ) yes no) => (First yes no) 751(EQ (FlagLT_ULT) yes no) => (First no yes) 752(EQ (FlagLT_UGT) yes no) => (First no yes) 753(EQ (FlagGT_ULT) yes no) => (First no yes) 754(EQ (FlagGT_UGT) yes no) => (First no yes) 755 756(NE (FlagEQ) yes no) => (First no yes) 757(NE (FlagLT_ULT) yes no) => (First yes no) 758(NE (FlagLT_UGT) yes no) => (First yes no) 759(NE (FlagGT_ULT) yes no) => (First yes no) 760(NE (FlagGT_UGT) yes no) => (First yes no) 761 762(LT (FlagEQ) yes no) => (First no yes) 763(LT (FlagLT_ULT) yes no) => (First yes no) 764(LT (FlagLT_UGT) yes no) => (First yes no) 765(LT (FlagGT_ULT) yes no) => (First no yes) 766(LT (FlagGT_UGT) yes no) => (First no yes) 767 768(LE (FlagEQ) yes no) => (First yes no) 769(LE (FlagLT_ULT) yes no) => (First yes no) 770(LE (FlagLT_UGT) yes no) => (First yes no) 771(LE (FlagGT_ULT) yes no) => (First no yes) 772(LE (FlagGT_UGT) yes no) => (First no yes) 773 774(GT (FlagEQ) yes no) => (First no yes) 775(GT (FlagLT_ULT) yes no) => (First no yes) 776(GT (FlagLT_UGT) yes no) => (First no yes) 777(GT (FlagGT_ULT) yes no) => (First yes no) 778(GT (FlagGT_UGT) yes no) => (First yes no) 779 780(GE (FlagEQ) yes no) => (First yes no) 781(GE (FlagLT_ULT) yes no) => (First no yes) 782(GE (FlagLT_UGT) yes no) => (First no yes) 783(GE (FlagGT_ULT) yes no) => (First yes no) 784(GE (FlagGT_UGT) yes no) => (First yes no) 785 786(ULT (FlagEQ) yes no) => (First no yes) 787(ULT (FlagLT_ULT) yes no) => (First yes no) 788(ULT (FlagLT_UGT) yes no) => (First no yes) 789(ULT (FlagGT_ULT) yes no) => (First yes no) 790(ULT (FlagGT_UGT) yes no) => (First no yes) 791 792(ULE (FlagEQ) yes no) => (First yes no) 793(ULE (FlagLT_ULT) yes no) => (First yes no) 794(ULE (FlagLT_UGT) yes no) => (First no yes) 795(ULE (FlagGT_ULT) yes no) => (First yes no) 796(ULE (FlagGT_UGT) yes no) => (First no yes) 797 798(UGT (FlagEQ) yes no) => (First no yes) 799(UGT (FlagLT_ULT) yes no) => (First no yes) 800(UGT (FlagLT_UGT) yes no) => (First yes no) 801(UGT (FlagGT_ULT) yes no) => (First no yes) 802(UGT (FlagGT_UGT) yes no) => (First yes no) 803 804(UGE (FlagEQ) yes no) => (First yes no) 805(UGE (FlagLT_ULT) yes no) => (First no yes) 806(UGE (FlagLT_UGT) yes no) => (First yes no) 807(UGE (FlagGT_ULT) yes no) => (First no yes) 808(UGE (FlagGT_UGT) yes no) => (First yes no) 809 810// Absorb flag constants into SETxx ops. 811(SETEQ (FlagEQ)) => (MOVLconst [1]) 812(SETEQ (FlagLT_ULT)) => (MOVLconst [0]) 813(SETEQ (FlagLT_UGT)) => (MOVLconst [0]) 814(SETEQ (FlagGT_ULT)) => (MOVLconst [0]) 815(SETEQ (FlagGT_UGT)) => (MOVLconst [0]) 816 817(SETNE (FlagEQ)) => (MOVLconst [0]) 818(SETNE (FlagLT_ULT)) => (MOVLconst [1]) 819(SETNE (FlagLT_UGT)) => (MOVLconst [1]) 820(SETNE (FlagGT_ULT)) => (MOVLconst [1]) 821(SETNE (FlagGT_UGT)) => (MOVLconst [1]) 822 823(SETL (FlagEQ)) => (MOVLconst [0]) 824(SETL (FlagLT_ULT)) => (MOVLconst [1]) 825(SETL (FlagLT_UGT)) => (MOVLconst [1]) 826(SETL (FlagGT_ULT)) => (MOVLconst [0]) 827(SETL (FlagGT_UGT)) => (MOVLconst [0]) 828 829(SETLE (FlagEQ)) => (MOVLconst [1]) 830(SETLE (FlagLT_ULT)) => (MOVLconst [1]) 831(SETLE (FlagLT_UGT)) => (MOVLconst [1]) 832(SETLE (FlagGT_ULT)) => (MOVLconst [0]) 833(SETLE (FlagGT_UGT)) => (MOVLconst [0]) 834 835(SETG (FlagEQ)) => (MOVLconst [0]) 836(SETG (FlagLT_ULT)) => (MOVLconst [0]) 837(SETG (FlagLT_UGT)) => (MOVLconst [0]) 838(SETG (FlagGT_ULT)) => (MOVLconst [1]) 839(SETG (FlagGT_UGT)) => (MOVLconst [1]) 840 841(SETGE (FlagEQ)) => (MOVLconst [1]) 842(SETGE (FlagLT_ULT)) => (MOVLconst [0]) 843(SETGE (FlagLT_UGT)) => (MOVLconst [0]) 844(SETGE (FlagGT_ULT)) => (MOVLconst [1]) 845(SETGE (FlagGT_UGT)) => (MOVLconst [1]) 846 847(SETB (FlagEQ)) => (MOVLconst [0]) 848(SETB (FlagLT_ULT)) => (MOVLconst [1]) 849(SETB (FlagLT_UGT)) => (MOVLconst [0]) 850(SETB (FlagGT_ULT)) => (MOVLconst [1]) 851(SETB (FlagGT_UGT)) => (MOVLconst [0]) 852 853(SETBE (FlagEQ)) => (MOVLconst [1]) 854(SETBE (FlagLT_ULT)) => (MOVLconst [1]) 855(SETBE (FlagLT_UGT)) => (MOVLconst [0]) 856(SETBE (FlagGT_ULT)) => (MOVLconst [1]) 857(SETBE (FlagGT_UGT)) => (MOVLconst [0]) 858 859(SETA (FlagEQ)) => (MOVLconst [0]) 860(SETA (FlagLT_ULT)) => (MOVLconst [0]) 861(SETA (FlagLT_UGT)) => (MOVLconst [1]) 862(SETA (FlagGT_ULT)) => (MOVLconst [0]) 863(SETA (FlagGT_UGT)) => (MOVLconst [1]) 864 865(SETAE (FlagEQ)) => (MOVLconst [1]) 866(SETAE (FlagLT_ULT)) => (MOVLconst [0]) 867(SETAE (FlagLT_UGT)) => (MOVLconst [1]) 868(SETAE (FlagGT_ULT)) => (MOVLconst [0]) 869(SETAE (FlagGT_UGT)) => (MOVLconst [1]) 870 871// Remove redundant *const ops 872(ADDLconst [c] x) && c==0 => x 873(SUBLconst [c] x) && c==0 => x 874(ANDLconst [c] _) && c==0 => (MOVLconst [0]) 875(ANDLconst [c] x) && c==-1 => x 876(ORLconst [c] x) && c==0 => x 877(ORLconst [c] _) && c==-1 => (MOVLconst [-1]) 878(XORLconst [c] x) && c==0 => x 879// TODO: since we got rid of the W/B versions, we might miss 880// things like (ANDLconst [0x100] x) which were formerly 881// (ANDBconst [0] x). Probably doesn't happen very often. 882// If we cared, we might do: 883// (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 => (MOVLconst [0]) 884 885// Convert constant subtracts to constant adds 886(SUBLconst [c] x) => (ADDLconst [-c] x) 887 888// generic constant folding 889// TODO: more of this 890(ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d]) 891(ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x) 892(SARLconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)]) 893(SARWconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)]) 894(SARBconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)]) 895(NEGL (MOVLconst [c])) => (MOVLconst [-c]) 896(MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d]) 897(ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d]) 898(ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d]) 899(XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d]) 900(NOTL (MOVLconst [c])) => (MOVLconst [^c]) 901 902// generic simplifications 903// TODO: more of this 904(ADDL x (NEGL y)) => (SUBL x y) 905(SUBL x x) => (MOVLconst [0]) 906(ANDL x x) => x 907(ORL x x) => x 908(XORL x x) => (MOVLconst [0]) 909 910// checking AND against 0. 911(CMP(L|W|B)const l:(ANDL x y) [0]) && l.Uses==1 => (TEST(L|W|B) x y) 912(CMPLconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTLconst [c] x) 913(CMPWconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTWconst [int16(c)] x) 914(CMPBconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTBconst [int8(c)] x) 915 916// TEST %reg,%reg is shorter than CMP 917(CMP(L|W|B)const x [0]) => (TEST(L|W|B) x x) 918 919// Convert LEAL1 back to ADDL if we can 920(LEAL1 [0] {nil} x y) => (ADDL x y) 921 922// For PIC, break floating-point constant loading into two instructions so we have 923// a register to use for holding the address of the constant pool entry. 924(MOVSSconst [c]) && config.ctxt.Flag_shared => (MOVSSconst2 (MOVSSconst1 [c])) 925(MOVSDconst [c]) && config.ctxt.Flag_shared => (MOVSDconst2 (MOVSDconst1 [c])) 926 927(CMP(L|W|B) l:(MOV(L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l) && clobber(l) => (CMP(L|W|B)load {sym} [off] ptr x mem) 928(CMP(L|W|B) x l:(MOV(L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (InvertFlags (CMP(L|W|B)load {sym} [off] ptr x mem)) 929 930(CMP(L|W|B)const l:(MOV(L|W|B)load {sym} [off] ptr mem) [c]) 931 && l.Uses == 1 932 && clobber(l) => 933 @l.Block (CMP(L|W|B)constload {sym} [makeValAndOff(int32(c),off)] ptr mem) 934 935(CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem) 936(CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem) 937(CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem) 938 939(MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read8(sym, int64(off)))]) 940(MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) 941(MOVLload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) 942