1// cmd/7l/list.c and cmd/7l/sub.c from Vita Nuova. 2// https://bitbucket.org/plan9-from-bell-labs/9-cc/src/master/ 3// 4// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6// Portions Copyright © 1997-1999 Vita Nuova Limited 7// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8// Portions Copyright © 2004,2006 Bruce Ellis 9// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11// Portions Copyright © 2009 The Go Authors. All rights reserved. 12// 13// Permission is hereby granted, free of charge, to any person obtaining a copy 14// of this software and associated documentation files (the "Software"), to deal 15// in the Software without restriction, including without limitation the rights 16// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17// copies of the Software, and to permit persons to whom the Software is 18// furnished to do so, subject to the following conditions: 19// 20// The above copyright notice and this permission notice shall be included in 21// all copies or substantial portions of the Software. 22// 23// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29// THE SOFTWARE. 30 31package arm64 32 33import ( 34 "cmd/internal/obj" 35 "fmt" 36) 37 38var strcond = [16]string{ 39 "EQ", 40 "NE", 41 "HS", 42 "LO", 43 "MI", 44 "PL", 45 "VS", 46 "VC", 47 "HI", 48 "LS", 49 "GE", 50 "LT", 51 "GT", 52 "LE", 53 "AL", 54 "NV", 55} 56 57func init() { 58 obj.RegisterRegister(obj.RBaseARM64, REG_SPECIAL+1024, rconv) 59 obj.RegisterOpcode(obj.ABaseARM64, Anames) 60 obj.RegisterRegisterList(obj.RegListARM64Lo, obj.RegListARM64Hi, rlconv) 61 obj.RegisterOpSuffix("arm64", obj.CConvARM) 62 obj.RegisterSpecialOperands(int64(SPOP_BEGIN), int64(SPOP_END), SPCconv) 63} 64 65func arrange(a int) string { 66 switch a { 67 case ARNG_8B: 68 return "B8" 69 case ARNG_16B: 70 return "B16" 71 case ARNG_4H: 72 return "H4" 73 case ARNG_8H: 74 return "H8" 75 case ARNG_2S: 76 return "S2" 77 case ARNG_4S: 78 return "S4" 79 case ARNG_1D: 80 return "D1" 81 case ARNG_2D: 82 return "D2" 83 case ARNG_B: 84 return "B" 85 case ARNG_H: 86 return "H" 87 case ARNG_S: 88 return "S" 89 case ARNG_D: 90 return "D" 91 case ARNG_1Q: 92 return "Q1" 93 default: 94 return "" 95 } 96} 97 98func rconv(r int) string { 99 ext := (r >> 5) & 7 100 if r == REGG { 101 return "g" 102 } 103 switch { 104 case REG_R0 <= r && r <= REG_R30: 105 return fmt.Sprintf("R%d", r-REG_R0) 106 case r == REG_R31: 107 return "ZR" 108 case REG_F0 <= r && r <= REG_F31: 109 return fmt.Sprintf("F%d", r-REG_F0) 110 case REG_V0 <= r && r <= REG_V31: 111 return fmt.Sprintf("V%d", r-REG_V0) 112 case r == REGSP: 113 return "RSP" 114 case REG_UXTB <= r && r < REG_UXTH: 115 if ext != 0 { 116 return fmt.Sprintf("%s.UXTB<<%d", regname(r), ext) 117 } else { 118 return fmt.Sprintf("%s.UXTB", regname(r)) 119 } 120 case REG_UXTH <= r && r < REG_UXTW: 121 if ext != 0 { 122 return fmt.Sprintf("%s.UXTH<<%d", regname(r), ext) 123 } else { 124 return fmt.Sprintf("%s.UXTH", regname(r)) 125 } 126 case REG_UXTW <= r && r < REG_UXTX: 127 if ext != 0 { 128 return fmt.Sprintf("%s.UXTW<<%d", regname(r), ext) 129 } else { 130 return fmt.Sprintf("%s.UXTW", regname(r)) 131 } 132 case REG_UXTX <= r && r < REG_SXTB: 133 if ext != 0 { 134 return fmt.Sprintf("%s.UXTX<<%d", regname(r), ext) 135 } else { 136 return fmt.Sprintf("%s.UXTX", regname(r)) 137 } 138 case REG_SXTB <= r && r < REG_SXTH: 139 if ext != 0 { 140 return fmt.Sprintf("%s.SXTB<<%d", regname(r), ext) 141 } else { 142 return fmt.Sprintf("%s.SXTB", regname(r)) 143 } 144 case REG_SXTH <= r && r < REG_SXTW: 145 if ext != 0 { 146 return fmt.Sprintf("%s.SXTH<<%d", regname(r), ext) 147 } else { 148 return fmt.Sprintf("%s.SXTH", regname(r)) 149 } 150 case REG_SXTW <= r && r < REG_SXTX: 151 if ext != 0 { 152 return fmt.Sprintf("%s.SXTW<<%d", regname(r), ext) 153 } else { 154 return fmt.Sprintf("%s.SXTW", regname(r)) 155 } 156 case REG_SXTX <= r && r < REG_SPECIAL: 157 if ext != 0 { 158 return fmt.Sprintf("%s.SXTX<<%d", regname(r), ext) 159 } else { 160 return fmt.Sprintf("%s.SXTX", regname(r)) 161 } 162 // bits 0-4 indicate register, bits 5-7 indicate shift amount, bit 8 equals to 0. 163 case REG_LSL <= r && r < (REG_LSL+1<<8): 164 return fmt.Sprintf("R%d<<%d", r&31, (r>>5)&7) 165 case REG_ARNG <= r && r < REG_ELEM: 166 return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15)) 167 case REG_ELEM <= r && r < REG_ELEM_END: 168 return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15)) 169 } 170 // Return system register name. 171 name, _, _ := SysRegEnc(int16(r)) 172 if name != "" { 173 return name 174 } 175 return fmt.Sprintf("badreg(%d)", r) 176} 177 178func DRconv(a int) string { 179 if a >= C_NONE && a <= C_NCLASS { 180 return cnames7[a] 181 } 182 return "C_??" 183} 184 185func SPCconv(a int64) string { 186 spc := SpecialOperand(a) 187 if spc >= SPOP_BEGIN && spc < SPOP_END { 188 return fmt.Sprintf("%s", spc) 189 } 190 return "SPC_??" 191} 192 193func rlconv(list int64) string { 194 str := "" 195 196 // ARM64 register list follows ARM64 instruction decode schema 197 // | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... | 198 // +----+----+-----+---------+---------+-----+ 199 // | | Q | ... | opcode | size | ... | 200 201 firstReg := int(list & 31) 202 opcode := (list >> 12) & 15 203 var regCnt int 204 var t string 205 switch opcode { 206 case 0x7: 207 regCnt = 1 208 case 0xa: 209 regCnt = 2 210 case 0x6: 211 regCnt = 3 212 case 0x2: 213 regCnt = 4 214 default: 215 regCnt = -1 216 } 217 // Q:size 218 arng := ((list>>30)&1)<<2 | (list>>10)&3 219 switch arng { 220 case 0: 221 t = "B8" 222 case 4: 223 t = "B16" 224 case 1: 225 t = "H4" 226 case 5: 227 t = "H8" 228 case 2: 229 t = "S2" 230 case 6: 231 t = "S4" 232 case 3: 233 t = "D1" 234 case 7: 235 t = "D2" 236 } 237 for i := 0; i < regCnt; i++ { 238 if str == "" { 239 str += "[" 240 } else { 241 str += "," 242 } 243 str += fmt.Sprintf("V%d.", (firstReg+i)&31) 244 str += t 245 } 246 str += "]" 247 return str 248} 249 250func regname(r int) string { 251 if r&31 == 31 { 252 return "ZR" 253 } 254 return fmt.Sprintf("R%d", r&31) 255} 256