1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI__LINUX_MDIO_H__ 20 #define _UAPI__LINUX_MDIO_H__ 21 #include <linux/types.h> 22 #include <linux/mii.h> 23 #define MDIO_MMD_PMAPMD 1 24 #define MDIO_MMD_WIS 2 25 #define MDIO_MMD_PCS 3 26 #define MDIO_MMD_PHYXS 4 27 #define MDIO_MMD_DTEXS 5 28 #define MDIO_MMD_TC 6 29 #define MDIO_MMD_AN 7 30 #define MDIO_MMD_C22EXT 29 31 #define MDIO_MMD_VEND1 30 32 #define MDIO_MMD_VEND2 31 33 #define MDIO_CTRL1 MII_BMCR 34 #define MDIO_STAT1 MII_BMSR 35 #define MDIO_DEVID1 MII_PHYSID1 36 #define MDIO_DEVID2 MII_PHYSID2 37 #define MDIO_SPEED 4 38 #define MDIO_DEVS1 5 39 #define MDIO_DEVS2 6 40 #define MDIO_CTRL2 7 41 #define MDIO_STAT2 8 42 #define MDIO_PMA_TXDIS 9 43 #define MDIO_PMA_RXDET 10 44 #define MDIO_PMA_EXTABLE 11 45 #define MDIO_PKGID1 14 46 #define MDIO_PKGID2 15 47 #define MDIO_AN_ADVERTISE 16 48 #define MDIO_AN_LPA 19 49 #define MDIO_PCS_EEE_ABLE 20 50 #define MDIO_PCS_EEE_ABLE2 21 51 #define MDIO_PMA_NG_EXTABLE 21 52 #define MDIO_PCS_EEE_WK_ERR 22 53 #define MDIO_PHYXS_LNSTAT 24 54 #define MDIO_AN_EEE_ADV 60 55 #define MDIO_AN_EEE_LPABLE 61 56 #define MDIO_AN_EEE_ADV2 62 57 #define MDIO_AN_EEE_LPABLE2 63 58 #define MDIO_AN_CTRL2 64 59 #define MDIO_PMA_10GBT_SWAPPOL 130 60 #define MDIO_PMA_10GBT_TXPWR 131 61 #define MDIO_PMA_10GBT_SNR 133 62 #define MDIO_PMA_10GBR_FSRT_CSR 147 63 #define MDIO_PMA_10GBR_FECABLE 170 64 #define MDIO_PCS_10GBX_STAT1 24 65 #define MDIO_PCS_10GBRT_STAT1 32 66 #define MDIO_PCS_10GBRT_STAT2 33 67 #define MDIO_AN_10GBT_CTRL 32 68 #define MDIO_AN_10GBT_STAT 33 69 #define MDIO_B10L_PMA_CTRL 2294 70 #define MDIO_PMA_10T1L_STAT 2295 71 #define MDIO_PCS_10T1L_CTRL 2278 72 #define MDIO_PMA_PMD_BT1 18 73 #define MDIO_AN_T1_CTRL 512 74 #define MDIO_AN_T1_STAT 513 75 #define MDIO_AN_T1_ADV_L 514 76 #define MDIO_AN_T1_ADV_M 515 77 #define MDIO_AN_T1_ADV_H 516 78 #define MDIO_AN_T1_LP_L 517 79 #define MDIO_AN_T1_LP_M 518 80 #define MDIO_AN_T1_LP_H 519 81 #define MDIO_PMA_PMD_BT1_CTRL 2100 82 #define MDIO_PMA_LASI_RXCTRL 0x9000 83 #define MDIO_PMA_LASI_TXCTRL 0x9001 84 #define MDIO_PMA_LASI_CTRL 0x9002 85 #define MDIO_PMA_LASI_RXSTAT 0x9003 86 #define MDIO_PMA_LASI_TXSTAT 0x9004 87 #define MDIO_PMA_LASI_STAT 0x9005 88 #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) 89 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) 90 #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX 91 #define MDIO_CTRL1_LPOWER BMCR_PDOWN 92 #define MDIO_CTRL1_RESET BMCR_RESET 93 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 94 #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 95 #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 96 #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK 97 #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK 98 #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART 99 #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE 100 #define MDIO_AN_CTRL1_XNP 0x2000 101 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 102 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 103 #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) 104 #define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) 105 #define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) 106 #define MDIO_STAT1_LPOWERABLE 0x0002 107 #define MDIO_STAT1_LSTATUS BMSR_LSTATUS 108 #define MDIO_STAT1_FAULT 0x0080 109 #define MDIO_AN_STAT1_LPABLE 0x0001 110 #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE 111 #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT 112 #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE 113 #define MDIO_AN_STAT1_PAGE 0x0040 114 #define MDIO_AN_STAT1_XNP 0x0080 115 #define MDIO_SPEED_10G 0x0001 116 #define MDIO_PMA_SPEED_2B 0x0002 117 #define MDIO_PMA_SPEED_10P 0x0004 118 #define MDIO_PMA_SPEED_1000 0x0010 119 #define MDIO_PMA_SPEED_100 0x0020 120 #define MDIO_PMA_SPEED_10 0x0040 121 #define MDIO_PCS_SPEED_10P2B 0x0002 122 #define MDIO_PCS_SPEED_2_5G 0x0040 123 #define MDIO_PCS_SPEED_5G 0x0080 124 #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) 125 #define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0) 126 #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) 127 #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) 128 #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) 129 #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) 130 #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) 131 #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) 132 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) 133 #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) 134 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) 135 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) 136 #define MDIO_PMA_CTRL2_TYPE 0x000f 137 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 138 #define MDIO_PMA_CTRL2_10GBEW 0x0001 139 #define MDIO_PMA_CTRL2_10GBLW 0x0002 140 #define MDIO_PMA_CTRL2_10GBSW 0x0003 141 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 142 #define MDIO_PMA_CTRL2_10GBER 0x0005 143 #define MDIO_PMA_CTRL2_10GBLR 0x0006 144 #define MDIO_PMA_CTRL2_10GBSR 0x0007 145 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 146 #define MDIO_PMA_CTRL2_10GBT 0x0009 147 #define MDIO_PMA_CTRL2_10GBKX4 0x000a 148 #define MDIO_PMA_CTRL2_10GBKR 0x000b 149 #define MDIO_PMA_CTRL2_1000BT 0x000c 150 #define MDIO_PMA_CTRL2_1000BKX 0x000d 151 #define MDIO_PMA_CTRL2_100BTX 0x000e 152 #define MDIO_PMA_CTRL2_10BT 0x000f 153 #define MDIO_PMA_CTRL2_2_5GBT 0x0030 154 #define MDIO_PMA_CTRL2_5GBT 0x0031 155 #define MDIO_PMA_CTRL2_BASET1 0x003D 156 #define MDIO_PCS_CTRL2_TYPE 0x0003 157 #define MDIO_PCS_CTRL2_10GBR 0x0000 158 #define MDIO_PCS_CTRL2_10GBX 0x0001 159 #define MDIO_PCS_CTRL2_10GBW 0x0002 160 #define MDIO_PCS_CTRL2_10GBT 0x0003 161 #define MDIO_STAT2_RXFAULT 0x0400 162 #define MDIO_STAT2_TXFAULT 0x0800 163 #define MDIO_STAT2_DEVPRST 0xc000 164 #define MDIO_STAT2_DEVPRST_VAL 0x8000 165 #define MDIO_PMA_STAT2_LBABLE 0x0001 166 #define MDIO_PMA_STAT2_10GBEW 0x0002 167 #define MDIO_PMA_STAT2_10GBLW 0x0004 168 #define MDIO_PMA_STAT2_10GBSW 0x0008 169 #define MDIO_PMA_STAT2_10GBLX4 0x0010 170 #define MDIO_PMA_STAT2_10GBER 0x0020 171 #define MDIO_PMA_STAT2_10GBLR 0x0040 172 #define MDIO_PMA_STAT2_10GBSR 0x0080 173 #define MDIO_PMD_STAT2_TXDISAB 0x0100 174 #define MDIO_PMA_STAT2_EXTABLE 0x0200 175 #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 176 #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 177 #define MDIO_PCS_STAT2_10GBR 0x0001 178 #define MDIO_PCS_STAT2_10GBX 0x0002 179 #define MDIO_PCS_STAT2_10GBW 0x0004 180 #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 181 #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 182 #define MDIO_PMD_TXDIS_GLOBAL 0x0001 183 #define MDIO_PMD_TXDIS_0 0x0002 184 #define MDIO_PMD_TXDIS_1 0x0004 185 #define MDIO_PMD_TXDIS_2 0x0008 186 #define MDIO_PMD_TXDIS_3 0x0010 187 #define MDIO_PMD_RXDET_GLOBAL 0x0001 188 #define MDIO_PMD_RXDET_0 0x0002 189 #define MDIO_PMD_RXDET_1 0x0004 190 #define MDIO_PMD_RXDET_2 0x0008 191 #define MDIO_PMD_RXDET_3 0x0010 192 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 193 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 194 #define MDIO_PMA_EXTABLE_10GBT 0x0004 195 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 196 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 197 #define MDIO_PMA_EXTABLE_1000BT 0x0020 198 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 199 #define MDIO_PMA_EXTABLE_100BTX 0x0080 200 #define MDIO_PMA_EXTABLE_10BT 0x0100 201 #define MDIO_PMA_EXTABLE_BT1 0x0800 202 #define MDIO_PMA_EXTABLE_NBT 0x4000 203 #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 204 #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 205 #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 206 #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 207 #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 208 #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 209 #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 210 #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 211 #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 212 #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 213 #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 214 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 215 #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 216 #define MDIO_PMA_10GBT_SNR_MAX 127 217 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 218 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 219 #define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001 220 #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 221 #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff 222 #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 223 #define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 224 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 225 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 226 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 227 #define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 228 #define MDIO_AN_10GBT_STAT_LP5G 0x0040 229 #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 230 #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 231 #define MDIO_AN_10GBT_STAT_LP10G 0x0800 232 #define MDIO_AN_10GBT_STAT_REMOK 0x1000 233 #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 234 #define MDIO_AN_10GBT_STAT_MS 0x4000 235 #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 236 #define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001 237 #define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400 238 #define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800 239 #define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000 240 #define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000 241 #define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000 242 #define MDIO_PMA_10T1L_STAT_LINK 0x0001 243 #define MDIO_PMA_10T1L_STAT_FAULT 0x0002 244 #define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 245 #define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 246 #define MDIO_PMA_10T1L_STAT_EEE 0x0400 247 #define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 248 #define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000 249 #define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 250 #define MDIO_PCS_10T1L_CTRL_LB 0x4000 251 #define MDIO_PCS_10T1L_CTRL_RESET 0x8000 252 #define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 253 #define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP 254 #define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM 255 #define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000 256 #define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT 257 #define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK 258 #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE 259 #define MDIO_AN_T1_ADV_M_B10L 0x4000 260 #define MDIO_AN_T1_ADV_M_MST 0x0010 261 #define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 262 #define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000 263 #define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP 264 #define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM 265 #define MDIO_AN_T1_LP_L_FORCE_MS 0x1000 266 #define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT 267 #define MDIO_AN_T1_LP_L_ACK LPA_LPACK 268 #define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE 269 #define MDIO_AN_T1_LP_M_MST 0x0010 270 #define MDIO_AN_T1_LP_M_B10L 0x4000 271 #define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 272 #define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 273 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 274 #define MDIO_AN_EEE_ADV_100TX 0x0002 275 #define MDIO_AN_EEE_ADV_1000T 0x0004 276 #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX 277 #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T 278 #define MDIO_EEE_10GT 0x0008 279 #define MDIO_EEE_1000KX 0x0010 280 #define MDIO_EEE_10GKX4 0x0020 281 #define MDIO_EEE_10GKR 0x0040 282 #define MDIO_EEE_40GR_FW 0x0100 283 #define MDIO_EEE_40GR_DS 0x0200 284 #define MDIO_EEE_100GR_FW 0x1000 285 #define MDIO_EEE_100GR_DS 0x2000 286 #define MDIO_EEE_2_5GT 0x0001 287 #define MDIO_EEE_5GT 0x0002 288 #define MDIO_AN_THP_BP2_5GT 0x0008 289 #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 290 #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 291 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 292 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 293 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 294 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 295 #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 296 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 297 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 298 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 299 #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 300 #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 301 #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 302 #define MDIO_PMA_LASI_LSALARM 0x0001 303 #define MDIO_PMA_LASI_TXALARM 0x0002 304 #define MDIO_PMA_LASI_RXALARM 0x0004 305 #define MDIO_PHY_ID_C45 0x8000 306 #define MDIO_PHY_ID_PRTAD 0x03e0 307 #define MDIO_PHY_ID_DEVAD 0x001f 308 #define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) 309 #define MDIO_USXGMII_EEE_CLK_STP 0x0080 310 #define MDIO_USXGMII_EEE 0x0100 311 #define MDIO_USXGMII_SPD_MASK 0x0e00 312 #define MDIO_USXGMII_FULL_DUPLEX 0x1000 313 #define MDIO_USXGMII_DPX_SPD_MASK 0x1e00 314 #define MDIO_USXGMII_10 0x0000 315 #define MDIO_USXGMII_10HALF 0x0000 316 #define MDIO_USXGMII_10FULL 0x1000 317 #define MDIO_USXGMII_100 0x0200 318 #define MDIO_USXGMII_100HALF 0x0200 319 #define MDIO_USXGMII_100FULL 0x1200 320 #define MDIO_USXGMII_1000 0x0400 321 #define MDIO_USXGMII_1000HALF 0x0400 322 #define MDIO_USXGMII_1000FULL 0x1400 323 #define MDIO_USXGMII_10G 0x0600 324 #define MDIO_USXGMII_10GHALF 0x0600 325 #define MDIO_USXGMII_10GFULL 0x1600 326 #define MDIO_USXGMII_2500 0x0800 327 #define MDIO_USXGMII_2500HALF 0x0800 328 #define MDIO_USXGMII_2500FULL 0x1800 329 #define MDIO_USXGMII_5000 0x0a00 330 #define MDIO_USXGMII_5000HALF 0x0a00 331 #define MDIO_USXGMII_5000FULL 0x1a00 332 #define MDIO_USXGMII_LINK 0x8000 333 #endif 334