1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef HABANALABS_H_ 20 #define HABANALABS_H_ 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 24 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 27 #define TS_MAX_ELEMENTS_NUM (1 << 20) 28 enum goya_queue_id { 29 GOYA_QUEUE_ID_DMA_0 = 0, 30 GOYA_QUEUE_ID_DMA_1 = 1, 31 GOYA_QUEUE_ID_DMA_2 = 2, 32 GOYA_QUEUE_ID_DMA_3 = 3, 33 GOYA_QUEUE_ID_DMA_4 = 4, 34 GOYA_QUEUE_ID_CPU_PQ = 5, 35 GOYA_QUEUE_ID_MME = 6, 36 GOYA_QUEUE_ID_TPC0 = 7, 37 GOYA_QUEUE_ID_TPC1 = 8, 38 GOYA_QUEUE_ID_TPC2 = 9, 39 GOYA_QUEUE_ID_TPC3 = 10, 40 GOYA_QUEUE_ID_TPC4 = 11, 41 GOYA_QUEUE_ID_TPC5 = 12, 42 GOYA_QUEUE_ID_TPC6 = 13, 43 GOYA_QUEUE_ID_TPC7 = 14, 44 GOYA_QUEUE_ID_SIZE 45 }; 46 enum gaudi_queue_id { 47 GAUDI_QUEUE_ID_DMA_0_0 = 0, 48 GAUDI_QUEUE_ID_DMA_0_1 = 1, 49 GAUDI_QUEUE_ID_DMA_0_2 = 2, 50 GAUDI_QUEUE_ID_DMA_0_3 = 3, 51 GAUDI_QUEUE_ID_DMA_1_0 = 4, 52 GAUDI_QUEUE_ID_DMA_1_1 = 5, 53 GAUDI_QUEUE_ID_DMA_1_2 = 6, 54 GAUDI_QUEUE_ID_DMA_1_3 = 7, 55 GAUDI_QUEUE_ID_CPU_PQ = 8, 56 GAUDI_QUEUE_ID_DMA_2_0 = 9, 57 GAUDI_QUEUE_ID_DMA_2_1 = 10, 58 GAUDI_QUEUE_ID_DMA_2_2 = 11, 59 GAUDI_QUEUE_ID_DMA_2_3 = 12, 60 GAUDI_QUEUE_ID_DMA_3_0 = 13, 61 GAUDI_QUEUE_ID_DMA_3_1 = 14, 62 GAUDI_QUEUE_ID_DMA_3_2 = 15, 63 GAUDI_QUEUE_ID_DMA_3_3 = 16, 64 GAUDI_QUEUE_ID_DMA_4_0 = 17, 65 GAUDI_QUEUE_ID_DMA_4_1 = 18, 66 GAUDI_QUEUE_ID_DMA_4_2 = 19, 67 GAUDI_QUEUE_ID_DMA_4_3 = 20, 68 GAUDI_QUEUE_ID_DMA_5_0 = 21, 69 GAUDI_QUEUE_ID_DMA_5_1 = 22, 70 GAUDI_QUEUE_ID_DMA_5_2 = 23, 71 GAUDI_QUEUE_ID_DMA_5_3 = 24, 72 GAUDI_QUEUE_ID_DMA_6_0 = 25, 73 GAUDI_QUEUE_ID_DMA_6_1 = 26, 74 GAUDI_QUEUE_ID_DMA_6_2 = 27, 75 GAUDI_QUEUE_ID_DMA_6_3 = 28, 76 GAUDI_QUEUE_ID_DMA_7_0 = 29, 77 GAUDI_QUEUE_ID_DMA_7_1 = 30, 78 GAUDI_QUEUE_ID_DMA_7_2 = 31, 79 GAUDI_QUEUE_ID_DMA_7_3 = 32, 80 GAUDI_QUEUE_ID_MME_0_0 = 33, 81 GAUDI_QUEUE_ID_MME_0_1 = 34, 82 GAUDI_QUEUE_ID_MME_0_2 = 35, 83 GAUDI_QUEUE_ID_MME_0_3 = 36, 84 GAUDI_QUEUE_ID_MME_1_0 = 37, 85 GAUDI_QUEUE_ID_MME_1_1 = 38, 86 GAUDI_QUEUE_ID_MME_1_2 = 39, 87 GAUDI_QUEUE_ID_MME_1_3 = 40, 88 GAUDI_QUEUE_ID_TPC_0_0 = 41, 89 GAUDI_QUEUE_ID_TPC_0_1 = 42, 90 GAUDI_QUEUE_ID_TPC_0_2 = 43, 91 GAUDI_QUEUE_ID_TPC_0_3 = 44, 92 GAUDI_QUEUE_ID_TPC_1_0 = 45, 93 GAUDI_QUEUE_ID_TPC_1_1 = 46, 94 GAUDI_QUEUE_ID_TPC_1_2 = 47, 95 GAUDI_QUEUE_ID_TPC_1_3 = 48, 96 GAUDI_QUEUE_ID_TPC_2_0 = 49, 97 GAUDI_QUEUE_ID_TPC_2_1 = 50, 98 GAUDI_QUEUE_ID_TPC_2_2 = 51, 99 GAUDI_QUEUE_ID_TPC_2_3 = 52, 100 GAUDI_QUEUE_ID_TPC_3_0 = 53, 101 GAUDI_QUEUE_ID_TPC_3_1 = 54, 102 GAUDI_QUEUE_ID_TPC_3_2 = 55, 103 GAUDI_QUEUE_ID_TPC_3_3 = 56, 104 GAUDI_QUEUE_ID_TPC_4_0 = 57, 105 GAUDI_QUEUE_ID_TPC_4_1 = 58, 106 GAUDI_QUEUE_ID_TPC_4_2 = 59, 107 GAUDI_QUEUE_ID_TPC_4_3 = 60, 108 GAUDI_QUEUE_ID_TPC_5_0 = 61, 109 GAUDI_QUEUE_ID_TPC_5_1 = 62, 110 GAUDI_QUEUE_ID_TPC_5_2 = 63, 111 GAUDI_QUEUE_ID_TPC_5_3 = 64, 112 GAUDI_QUEUE_ID_TPC_6_0 = 65, 113 GAUDI_QUEUE_ID_TPC_6_1 = 66, 114 GAUDI_QUEUE_ID_TPC_6_2 = 67, 115 GAUDI_QUEUE_ID_TPC_6_3 = 68, 116 GAUDI_QUEUE_ID_TPC_7_0 = 69, 117 GAUDI_QUEUE_ID_TPC_7_1 = 70, 118 GAUDI_QUEUE_ID_TPC_7_2 = 71, 119 GAUDI_QUEUE_ID_TPC_7_3 = 72, 120 GAUDI_QUEUE_ID_NIC_0_0 = 73, 121 GAUDI_QUEUE_ID_NIC_0_1 = 74, 122 GAUDI_QUEUE_ID_NIC_0_2 = 75, 123 GAUDI_QUEUE_ID_NIC_0_3 = 76, 124 GAUDI_QUEUE_ID_NIC_1_0 = 77, 125 GAUDI_QUEUE_ID_NIC_1_1 = 78, 126 GAUDI_QUEUE_ID_NIC_1_2 = 79, 127 GAUDI_QUEUE_ID_NIC_1_3 = 80, 128 GAUDI_QUEUE_ID_NIC_2_0 = 81, 129 GAUDI_QUEUE_ID_NIC_2_1 = 82, 130 GAUDI_QUEUE_ID_NIC_2_2 = 83, 131 GAUDI_QUEUE_ID_NIC_2_3 = 84, 132 GAUDI_QUEUE_ID_NIC_3_0 = 85, 133 GAUDI_QUEUE_ID_NIC_3_1 = 86, 134 GAUDI_QUEUE_ID_NIC_3_2 = 87, 135 GAUDI_QUEUE_ID_NIC_3_3 = 88, 136 GAUDI_QUEUE_ID_NIC_4_0 = 89, 137 GAUDI_QUEUE_ID_NIC_4_1 = 90, 138 GAUDI_QUEUE_ID_NIC_4_2 = 91, 139 GAUDI_QUEUE_ID_NIC_4_3 = 92, 140 GAUDI_QUEUE_ID_NIC_5_0 = 93, 141 GAUDI_QUEUE_ID_NIC_5_1 = 94, 142 GAUDI_QUEUE_ID_NIC_5_2 = 95, 143 GAUDI_QUEUE_ID_NIC_5_3 = 96, 144 GAUDI_QUEUE_ID_NIC_6_0 = 97, 145 GAUDI_QUEUE_ID_NIC_6_1 = 98, 146 GAUDI_QUEUE_ID_NIC_6_2 = 99, 147 GAUDI_QUEUE_ID_NIC_6_3 = 100, 148 GAUDI_QUEUE_ID_NIC_7_0 = 101, 149 GAUDI_QUEUE_ID_NIC_7_1 = 102, 150 GAUDI_QUEUE_ID_NIC_7_2 = 103, 151 GAUDI_QUEUE_ID_NIC_7_3 = 104, 152 GAUDI_QUEUE_ID_NIC_8_0 = 105, 153 GAUDI_QUEUE_ID_NIC_8_1 = 106, 154 GAUDI_QUEUE_ID_NIC_8_2 = 107, 155 GAUDI_QUEUE_ID_NIC_8_3 = 108, 156 GAUDI_QUEUE_ID_NIC_9_0 = 109, 157 GAUDI_QUEUE_ID_NIC_9_1 = 110, 158 GAUDI_QUEUE_ID_NIC_9_2 = 111, 159 GAUDI_QUEUE_ID_NIC_9_3 = 112, 160 GAUDI_QUEUE_ID_SIZE 161 }; 162 enum gaudi2_queue_id { 163 GAUDI2_QUEUE_ID_PDMA_0_0 = 0, 164 GAUDI2_QUEUE_ID_PDMA_0_1 = 1, 165 GAUDI2_QUEUE_ID_PDMA_0_2 = 2, 166 GAUDI2_QUEUE_ID_PDMA_0_3 = 3, 167 GAUDI2_QUEUE_ID_PDMA_1_0 = 4, 168 GAUDI2_QUEUE_ID_PDMA_1_1 = 5, 169 GAUDI2_QUEUE_ID_PDMA_1_2 = 6, 170 GAUDI2_QUEUE_ID_PDMA_1_3 = 7, 171 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8, 172 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9, 173 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10, 174 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11, 175 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12, 176 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13, 177 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14, 178 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15, 179 GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16, 180 GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17, 181 GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18, 182 GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19, 183 GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20, 184 GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21, 185 GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22, 186 GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23, 187 GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24, 188 GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25, 189 GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26, 190 GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27, 191 GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28, 192 GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29, 193 GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30, 194 GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31, 195 GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32, 196 GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33, 197 GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34, 198 GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35, 199 GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36, 200 GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37, 201 GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38, 202 GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39, 203 GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40, 204 GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41, 205 GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42, 206 GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43, 207 GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44, 208 GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45, 209 GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46, 210 GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47, 211 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48, 212 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49, 213 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50, 214 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51, 215 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52, 216 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53, 217 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54, 218 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55, 219 GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56, 220 GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57, 221 GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58, 222 GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59, 223 GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60, 224 GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61, 225 GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62, 226 GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63, 227 GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64, 228 GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65, 229 GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66, 230 GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67, 231 GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68, 232 GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69, 233 GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70, 234 GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71, 235 GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72, 236 GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73, 237 GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74, 238 GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75, 239 GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76, 240 GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77, 241 GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78, 242 GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79, 243 GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80, 244 GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81, 245 GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82, 246 GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83, 247 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84, 248 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85, 249 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86, 250 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87, 251 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88, 252 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89, 253 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90, 254 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91, 255 GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92, 256 GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93, 257 GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94, 258 GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95, 259 GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96, 260 GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97, 261 GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98, 262 GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99, 263 GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100, 264 GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101, 265 GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102, 266 GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103, 267 GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104, 268 GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105, 269 GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106, 270 GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107, 271 GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108, 272 GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109, 273 GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110, 274 GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111, 275 GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112, 276 GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113, 277 GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114, 278 GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115, 279 GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116, 280 GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117, 281 GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118, 282 GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119, 283 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120, 284 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121, 285 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122, 286 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123, 287 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124, 288 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125, 289 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126, 290 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127, 291 GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128, 292 GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129, 293 GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130, 294 GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131, 295 GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132, 296 GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133, 297 GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134, 298 GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135, 299 GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136, 300 GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137, 301 GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138, 302 GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139, 303 GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140, 304 GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141, 305 GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142, 306 GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143, 307 GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144, 308 GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145, 309 GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146, 310 GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147, 311 GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148, 312 GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149, 313 GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150, 314 GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151, 315 GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152, 316 GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153, 317 GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154, 318 GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155, 319 GAUDI2_QUEUE_ID_NIC_0_0 = 156, 320 GAUDI2_QUEUE_ID_NIC_0_1 = 157, 321 GAUDI2_QUEUE_ID_NIC_0_2 = 158, 322 GAUDI2_QUEUE_ID_NIC_0_3 = 159, 323 GAUDI2_QUEUE_ID_NIC_1_0 = 160, 324 GAUDI2_QUEUE_ID_NIC_1_1 = 161, 325 GAUDI2_QUEUE_ID_NIC_1_2 = 162, 326 GAUDI2_QUEUE_ID_NIC_1_3 = 163, 327 GAUDI2_QUEUE_ID_NIC_2_0 = 164, 328 GAUDI2_QUEUE_ID_NIC_2_1 = 165, 329 GAUDI2_QUEUE_ID_NIC_2_2 = 166, 330 GAUDI2_QUEUE_ID_NIC_2_3 = 167, 331 GAUDI2_QUEUE_ID_NIC_3_0 = 168, 332 GAUDI2_QUEUE_ID_NIC_3_1 = 169, 333 GAUDI2_QUEUE_ID_NIC_3_2 = 170, 334 GAUDI2_QUEUE_ID_NIC_3_3 = 171, 335 GAUDI2_QUEUE_ID_NIC_4_0 = 172, 336 GAUDI2_QUEUE_ID_NIC_4_1 = 173, 337 GAUDI2_QUEUE_ID_NIC_4_2 = 174, 338 GAUDI2_QUEUE_ID_NIC_4_3 = 175, 339 GAUDI2_QUEUE_ID_NIC_5_0 = 176, 340 GAUDI2_QUEUE_ID_NIC_5_1 = 177, 341 GAUDI2_QUEUE_ID_NIC_5_2 = 178, 342 GAUDI2_QUEUE_ID_NIC_5_3 = 179, 343 GAUDI2_QUEUE_ID_NIC_6_0 = 180, 344 GAUDI2_QUEUE_ID_NIC_6_1 = 181, 345 GAUDI2_QUEUE_ID_NIC_6_2 = 182, 346 GAUDI2_QUEUE_ID_NIC_6_3 = 183, 347 GAUDI2_QUEUE_ID_NIC_7_0 = 184, 348 GAUDI2_QUEUE_ID_NIC_7_1 = 185, 349 GAUDI2_QUEUE_ID_NIC_7_2 = 186, 350 GAUDI2_QUEUE_ID_NIC_7_3 = 187, 351 GAUDI2_QUEUE_ID_NIC_8_0 = 188, 352 GAUDI2_QUEUE_ID_NIC_8_1 = 189, 353 GAUDI2_QUEUE_ID_NIC_8_2 = 190, 354 GAUDI2_QUEUE_ID_NIC_8_3 = 191, 355 GAUDI2_QUEUE_ID_NIC_9_0 = 192, 356 GAUDI2_QUEUE_ID_NIC_9_1 = 193, 357 GAUDI2_QUEUE_ID_NIC_9_2 = 194, 358 GAUDI2_QUEUE_ID_NIC_9_3 = 195, 359 GAUDI2_QUEUE_ID_NIC_10_0 = 196, 360 GAUDI2_QUEUE_ID_NIC_10_1 = 197, 361 GAUDI2_QUEUE_ID_NIC_10_2 = 198, 362 GAUDI2_QUEUE_ID_NIC_10_3 = 199, 363 GAUDI2_QUEUE_ID_NIC_11_0 = 200, 364 GAUDI2_QUEUE_ID_NIC_11_1 = 201, 365 GAUDI2_QUEUE_ID_NIC_11_2 = 202, 366 GAUDI2_QUEUE_ID_NIC_11_3 = 203, 367 GAUDI2_QUEUE_ID_NIC_12_0 = 204, 368 GAUDI2_QUEUE_ID_NIC_12_1 = 205, 369 GAUDI2_QUEUE_ID_NIC_12_2 = 206, 370 GAUDI2_QUEUE_ID_NIC_12_3 = 207, 371 GAUDI2_QUEUE_ID_NIC_13_0 = 208, 372 GAUDI2_QUEUE_ID_NIC_13_1 = 209, 373 GAUDI2_QUEUE_ID_NIC_13_2 = 210, 374 GAUDI2_QUEUE_ID_NIC_13_3 = 211, 375 GAUDI2_QUEUE_ID_NIC_14_0 = 212, 376 GAUDI2_QUEUE_ID_NIC_14_1 = 213, 377 GAUDI2_QUEUE_ID_NIC_14_2 = 214, 378 GAUDI2_QUEUE_ID_NIC_14_3 = 215, 379 GAUDI2_QUEUE_ID_NIC_15_0 = 216, 380 GAUDI2_QUEUE_ID_NIC_15_1 = 217, 381 GAUDI2_QUEUE_ID_NIC_15_2 = 218, 382 GAUDI2_QUEUE_ID_NIC_15_3 = 219, 383 GAUDI2_QUEUE_ID_NIC_16_0 = 220, 384 GAUDI2_QUEUE_ID_NIC_16_1 = 221, 385 GAUDI2_QUEUE_ID_NIC_16_2 = 222, 386 GAUDI2_QUEUE_ID_NIC_16_3 = 223, 387 GAUDI2_QUEUE_ID_NIC_17_0 = 224, 388 GAUDI2_QUEUE_ID_NIC_17_1 = 225, 389 GAUDI2_QUEUE_ID_NIC_17_2 = 226, 390 GAUDI2_QUEUE_ID_NIC_17_3 = 227, 391 GAUDI2_QUEUE_ID_NIC_18_0 = 228, 392 GAUDI2_QUEUE_ID_NIC_18_1 = 229, 393 GAUDI2_QUEUE_ID_NIC_18_2 = 230, 394 GAUDI2_QUEUE_ID_NIC_18_3 = 231, 395 GAUDI2_QUEUE_ID_NIC_19_0 = 232, 396 GAUDI2_QUEUE_ID_NIC_19_1 = 233, 397 GAUDI2_QUEUE_ID_NIC_19_2 = 234, 398 GAUDI2_QUEUE_ID_NIC_19_3 = 235, 399 GAUDI2_QUEUE_ID_NIC_20_0 = 236, 400 GAUDI2_QUEUE_ID_NIC_20_1 = 237, 401 GAUDI2_QUEUE_ID_NIC_20_2 = 238, 402 GAUDI2_QUEUE_ID_NIC_20_3 = 239, 403 GAUDI2_QUEUE_ID_NIC_21_0 = 240, 404 GAUDI2_QUEUE_ID_NIC_21_1 = 241, 405 GAUDI2_QUEUE_ID_NIC_21_2 = 242, 406 GAUDI2_QUEUE_ID_NIC_21_3 = 243, 407 GAUDI2_QUEUE_ID_NIC_22_0 = 244, 408 GAUDI2_QUEUE_ID_NIC_22_1 = 245, 409 GAUDI2_QUEUE_ID_NIC_22_2 = 246, 410 GAUDI2_QUEUE_ID_NIC_22_3 = 247, 411 GAUDI2_QUEUE_ID_NIC_23_0 = 248, 412 GAUDI2_QUEUE_ID_NIC_23_1 = 249, 413 GAUDI2_QUEUE_ID_NIC_23_2 = 250, 414 GAUDI2_QUEUE_ID_NIC_23_3 = 251, 415 GAUDI2_QUEUE_ID_ROT_0_0 = 252, 416 GAUDI2_QUEUE_ID_ROT_0_1 = 253, 417 GAUDI2_QUEUE_ID_ROT_0_2 = 254, 418 GAUDI2_QUEUE_ID_ROT_0_3 = 255, 419 GAUDI2_QUEUE_ID_ROT_1_0 = 256, 420 GAUDI2_QUEUE_ID_ROT_1_1 = 257, 421 GAUDI2_QUEUE_ID_ROT_1_2 = 258, 422 GAUDI2_QUEUE_ID_ROT_1_3 = 259, 423 GAUDI2_QUEUE_ID_CPU_PQ = 260, 424 GAUDI2_QUEUE_ID_SIZE 425 }; 426 enum goya_engine_id { 427 GOYA_ENGINE_ID_DMA_0 = 0, 428 GOYA_ENGINE_ID_DMA_1, 429 GOYA_ENGINE_ID_DMA_2, 430 GOYA_ENGINE_ID_DMA_3, 431 GOYA_ENGINE_ID_DMA_4, 432 GOYA_ENGINE_ID_MME_0, 433 GOYA_ENGINE_ID_TPC_0, 434 GOYA_ENGINE_ID_TPC_1, 435 GOYA_ENGINE_ID_TPC_2, 436 GOYA_ENGINE_ID_TPC_3, 437 GOYA_ENGINE_ID_TPC_4, 438 GOYA_ENGINE_ID_TPC_5, 439 GOYA_ENGINE_ID_TPC_6, 440 GOYA_ENGINE_ID_TPC_7, 441 GOYA_ENGINE_ID_SIZE 442 }; 443 enum gaudi_engine_id { 444 GAUDI_ENGINE_ID_DMA_0 = 0, 445 GAUDI_ENGINE_ID_DMA_1, 446 GAUDI_ENGINE_ID_DMA_2, 447 GAUDI_ENGINE_ID_DMA_3, 448 GAUDI_ENGINE_ID_DMA_4, 449 GAUDI_ENGINE_ID_DMA_5, 450 GAUDI_ENGINE_ID_DMA_6, 451 GAUDI_ENGINE_ID_DMA_7, 452 GAUDI_ENGINE_ID_MME_0, 453 GAUDI_ENGINE_ID_MME_1, 454 GAUDI_ENGINE_ID_MME_2, 455 GAUDI_ENGINE_ID_MME_3, 456 GAUDI_ENGINE_ID_TPC_0, 457 GAUDI_ENGINE_ID_TPC_1, 458 GAUDI_ENGINE_ID_TPC_2, 459 GAUDI_ENGINE_ID_TPC_3, 460 GAUDI_ENGINE_ID_TPC_4, 461 GAUDI_ENGINE_ID_TPC_5, 462 GAUDI_ENGINE_ID_TPC_6, 463 GAUDI_ENGINE_ID_TPC_7, 464 GAUDI_ENGINE_ID_NIC_0, 465 GAUDI_ENGINE_ID_NIC_1, 466 GAUDI_ENGINE_ID_NIC_2, 467 GAUDI_ENGINE_ID_NIC_3, 468 GAUDI_ENGINE_ID_NIC_4, 469 GAUDI_ENGINE_ID_NIC_5, 470 GAUDI_ENGINE_ID_NIC_6, 471 GAUDI_ENGINE_ID_NIC_7, 472 GAUDI_ENGINE_ID_NIC_8, 473 GAUDI_ENGINE_ID_NIC_9, 474 GAUDI_ENGINE_ID_SIZE 475 }; 476 enum gaudi2_engine_id { 477 GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0, 478 GAUDI2_DCORE0_ENGINE_ID_EDMA_1, 479 GAUDI2_DCORE0_ENGINE_ID_MME, 480 GAUDI2_DCORE0_ENGINE_ID_TPC_0, 481 GAUDI2_DCORE0_ENGINE_ID_TPC_1, 482 GAUDI2_DCORE0_ENGINE_ID_TPC_2, 483 GAUDI2_DCORE0_ENGINE_ID_TPC_3, 484 GAUDI2_DCORE0_ENGINE_ID_TPC_4, 485 GAUDI2_DCORE0_ENGINE_ID_TPC_5, 486 GAUDI2_DCORE0_ENGINE_ID_DEC_0, 487 GAUDI2_DCORE0_ENGINE_ID_DEC_1, 488 GAUDI2_DCORE1_ENGINE_ID_EDMA_0, 489 GAUDI2_DCORE1_ENGINE_ID_EDMA_1, 490 GAUDI2_DCORE1_ENGINE_ID_MME, 491 GAUDI2_DCORE1_ENGINE_ID_TPC_0, 492 GAUDI2_DCORE1_ENGINE_ID_TPC_1, 493 GAUDI2_DCORE1_ENGINE_ID_TPC_2, 494 GAUDI2_DCORE1_ENGINE_ID_TPC_3, 495 GAUDI2_DCORE1_ENGINE_ID_TPC_4, 496 GAUDI2_DCORE1_ENGINE_ID_TPC_5, 497 GAUDI2_DCORE1_ENGINE_ID_DEC_0, 498 GAUDI2_DCORE1_ENGINE_ID_DEC_1, 499 GAUDI2_DCORE2_ENGINE_ID_EDMA_0, 500 GAUDI2_DCORE2_ENGINE_ID_EDMA_1, 501 GAUDI2_DCORE2_ENGINE_ID_MME, 502 GAUDI2_DCORE2_ENGINE_ID_TPC_0, 503 GAUDI2_DCORE2_ENGINE_ID_TPC_1, 504 GAUDI2_DCORE2_ENGINE_ID_TPC_2, 505 GAUDI2_DCORE2_ENGINE_ID_TPC_3, 506 GAUDI2_DCORE2_ENGINE_ID_TPC_4, 507 GAUDI2_DCORE2_ENGINE_ID_TPC_5, 508 GAUDI2_DCORE2_ENGINE_ID_DEC_0, 509 GAUDI2_DCORE2_ENGINE_ID_DEC_1, 510 GAUDI2_DCORE3_ENGINE_ID_EDMA_0, 511 GAUDI2_DCORE3_ENGINE_ID_EDMA_1, 512 GAUDI2_DCORE3_ENGINE_ID_MME, 513 GAUDI2_DCORE3_ENGINE_ID_TPC_0, 514 GAUDI2_DCORE3_ENGINE_ID_TPC_1, 515 GAUDI2_DCORE3_ENGINE_ID_TPC_2, 516 GAUDI2_DCORE3_ENGINE_ID_TPC_3, 517 GAUDI2_DCORE3_ENGINE_ID_TPC_4, 518 GAUDI2_DCORE3_ENGINE_ID_TPC_5, 519 GAUDI2_DCORE3_ENGINE_ID_DEC_0, 520 GAUDI2_DCORE3_ENGINE_ID_DEC_1, 521 GAUDI2_DCORE0_ENGINE_ID_TPC_6, 522 GAUDI2_ENGINE_ID_PDMA_0, 523 GAUDI2_ENGINE_ID_PDMA_1, 524 GAUDI2_ENGINE_ID_ROT_0, 525 GAUDI2_ENGINE_ID_ROT_1, 526 GAUDI2_PCIE_ENGINE_ID_DEC_0, 527 GAUDI2_PCIE_ENGINE_ID_DEC_1, 528 GAUDI2_ENGINE_ID_NIC0_0, 529 GAUDI2_ENGINE_ID_NIC0_1, 530 GAUDI2_ENGINE_ID_NIC1_0, 531 GAUDI2_ENGINE_ID_NIC1_1, 532 GAUDI2_ENGINE_ID_NIC2_0, 533 GAUDI2_ENGINE_ID_NIC2_1, 534 GAUDI2_ENGINE_ID_NIC3_0, 535 GAUDI2_ENGINE_ID_NIC3_1, 536 GAUDI2_ENGINE_ID_NIC4_0, 537 GAUDI2_ENGINE_ID_NIC4_1, 538 GAUDI2_ENGINE_ID_NIC5_0, 539 GAUDI2_ENGINE_ID_NIC5_1, 540 GAUDI2_ENGINE_ID_NIC6_0, 541 GAUDI2_ENGINE_ID_NIC6_1, 542 GAUDI2_ENGINE_ID_NIC7_0, 543 GAUDI2_ENGINE_ID_NIC7_1, 544 GAUDI2_ENGINE_ID_NIC8_0, 545 GAUDI2_ENGINE_ID_NIC8_1, 546 GAUDI2_ENGINE_ID_NIC9_0, 547 GAUDI2_ENGINE_ID_NIC9_1, 548 GAUDI2_ENGINE_ID_NIC10_0, 549 GAUDI2_ENGINE_ID_NIC10_1, 550 GAUDI2_ENGINE_ID_NIC11_0, 551 GAUDI2_ENGINE_ID_NIC11_1, 552 GAUDI2_ENGINE_ID_PCIE, 553 GAUDI2_ENGINE_ID_PSOC, 554 GAUDI2_ENGINE_ID_ARC_FARM, 555 GAUDI2_ENGINE_ID_KDMA, 556 GAUDI2_ENGINE_ID_SIZE 557 }; 558 enum hl_goya_pll_index { 559 HL_GOYA_CPU_PLL = 0, 560 HL_GOYA_IC_PLL, 561 HL_GOYA_MC_PLL, 562 HL_GOYA_MME_PLL, 563 HL_GOYA_PCI_PLL, 564 HL_GOYA_EMMC_PLL, 565 HL_GOYA_TPC_PLL, 566 HL_GOYA_PLL_MAX 567 }; 568 enum hl_gaudi_pll_index { 569 HL_GAUDI_CPU_PLL = 0, 570 HL_GAUDI_PCI_PLL, 571 HL_GAUDI_SRAM_PLL, 572 HL_GAUDI_HBM_PLL, 573 HL_GAUDI_NIC_PLL, 574 HL_GAUDI_DMA_PLL, 575 HL_GAUDI_MESH_PLL, 576 HL_GAUDI_MME_PLL, 577 HL_GAUDI_TPC_PLL, 578 HL_GAUDI_IF_PLL, 579 HL_GAUDI_PLL_MAX 580 }; 581 enum hl_gaudi2_pll_index { 582 HL_GAUDI2_CPU_PLL = 0, 583 HL_GAUDI2_PCI_PLL, 584 HL_GAUDI2_SRAM_PLL, 585 HL_GAUDI2_HBM_PLL, 586 HL_GAUDI2_NIC_PLL, 587 HL_GAUDI2_DMA_PLL, 588 HL_GAUDI2_MESH_PLL, 589 HL_GAUDI2_MME_PLL, 590 HL_GAUDI2_TPC_PLL, 591 HL_GAUDI2_IF_PLL, 592 HL_GAUDI2_VID_PLL, 593 HL_GAUDI2_MSS_PLL, 594 HL_GAUDI2_PLL_MAX 595 }; 596 enum hl_goya_dma_direction { 597 HL_DMA_HOST_TO_DRAM, 598 HL_DMA_HOST_TO_SRAM, 599 HL_DMA_DRAM_TO_SRAM, 600 HL_DMA_SRAM_TO_DRAM, 601 HL_DMA_SRAM_TO_HOST, 602 HL_DMA_DRAM_TO_HOST, 603 HL_DMA_DRAM_TO_DRAM, 604 HL_DMA_SRAM_TO_SRAM, 605 HL_DMA_ENUM_MAX 606 }; 607 enum hl_device_status { 608 HL_DEVICE_STATUS_OPERATIONAL, 609 HL_DEVICE_STATUS_IN_RESET, 610 HL_DEVICE_STATUS_MALFUNCTION, 611 HL_DEVICE_STATUS_NEEDS_RESET, 612 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 613 HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE, 614 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE 615 }; 616 enum hl_server_type { 617 HL_SERVER_TYPE_UNKNOWN = 0, 618 HL_SERVER_GAUDI_HLS1 = 1, 619 HL_SERVER_GAUDI_HLS1H = 2, 620 HL_SERVER_GAUDI_TYPE1 = 3, 621 HL_SERVER_GAUDI_TYPE2 = 4, 622 HL_SERVER_GAUDI2_HLS2 = 5 623 }; 624 #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) 625 #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) 626 #define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2) 627 #define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3) 628 #define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4) 629 #define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5) 630 #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6) 631 #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7) 632 #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8) 633 #define HL_INFO_HW_IP_INFO 0 634 #define HL_INFO_HW_EVENTS 1 635 #define HL_INFO_DRAM_USAGE 2 636 #define HL_INFO_HW_IDLE 3 637 #define HL_INFO_DEVICE_STATUS 4 638 #define HL_INFO_DEVICE_UTILIZATION 6 639 #define HL_INFO_HW_EVENTS_AGGREGATE 7 640 #define HL_INFO_CLK_RATE 8 641 #define HL_INFO_RESET_COUNT 9 642 #define HL_INFO_TIME_SYNC 10 643 #define HL_INFO_CS_COUNTERS 11 644 #define HL_INFO_PCI_COUNTERS 12 645 #define HL_INFO_CLK_THROTTLE_REASON 13 646 #define HL_INFO_SYNC_MANAGER 14 647 #define HL_INFO_TOTAL_ENERGY 15 648 #define HL_INFO_PLL_FREQUENCY 16 649 #define HL_INFO_POWER 17 650 #define HL_INFO_OPEN_STATS 18 651 #define HL_INFO_DRAM_REPLACED_ROWS 21 652 #define HL_INFO_DRAM_PENDING_ROWS 22 653 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 654 #define HL_INFO_CS_TIMEOUT_EVENT 24 655 #define HL_INFO_RAZWI_EVENT 25 656 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 657 #define HL_INFO_SECURED_ATTESTATION 27 658 #define HL_INFO_REGISTER_EVENTFD 28 659 #define HL_INFO_UNREGISTER_EVENTFD 29 660 #define HL_INFO_GET_EVENTS 30 661 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 662 #define HL_INFO_ENGINE_STATUS 32 663 #define HL_INFO_PAGE_FAULT_EVENT 33 664 #define HL_INFO_USER_MAPPINGS 34 665 #define HL_INFO_VERSION_MAX_LEN 128 666 #define HL_INFO_CARD_NAME_MAX_LEN 16 667 #define HL_ENGINES_DATA_MAX_SIZE SZ_1M 668 struct hl_info_hw_ip_info { 669 __u64 sram_base_address; 670 __u64 dram_base_address; 671 __u64 dram_size; 672 __u32 sram_size; 673 __u32 num_of_events; 674 __u32 device_id; 675 __u32 module_id; 676 __u32 decoder_enabled_mask; 677 __u16 first_available_interrupt_id; 678 __u16 server_type; 679 __u32 cpld_version; 680 __u32 psoc_pci_pll_nr; 681 __u32 psoc_pci_pll_nf; 682 __u32 psoc_pci_pll_od; 683 __u32 psoc_pci_pll_div_factor; 684 __u8 tpc_enabled_mask; 685 __u8 dram_enabled; 686 __u8 security_enabled; 687 __u8 mme_master_slave_mode; 688 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 689 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 690 __u64 tpc_enabled_mask_ext; 691 __u64 dram_page_size; 692 __u32 edma_enabled_mask; 693 __u16 number_of_user_interrupts; 694 __u16 pad2; 695 __u64 reserved4; 696 __u64 device_mem_alloc_default_page_size; 697 __u64 reserved5; 698 __u64 reserved6; 699 __u32 reserved7; 700 __u8 reserved8; 701 __u8 revision_id; 702 __u8 pad[2]; 703 }; 704 struct hl_info_dram_usage { 705 __u64 dram_free_mem; 706 __u64 ctx_dram_mem; 707 }; 708 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 4 709 struct hl_info_hw_idle { 710 __u32 is_idle; 711 __u32 busy_engines_mask; 712 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 713 }; 714 struct hl_info_device_status { 715 __u32 status; 716 __u32 pad; 717 }; 718 struct hl_info_device_utilization { 719 __u32 utilization; 720 __u32 pad; 721 }; 722 struct hl_info_clk_rate { 723 __u32 cur_clk_rate_mhz; 724 __u32 max_clk_rate_mhz; 725 }; 726 struct hl_info_reset_count { 727 __u32 hard_reset_cnt; 728 __u32 soft_reset_cnt; 729 }; 730 struct hl_info_time_sync { 731 __u64 device_time; 732 __u64 host_time; 733 }; 734 struct hl_info_pci_counters { 735 __u64 rx_throughput; 736 __u64 tx_throughput; 737 __u64 replay_cnt; 738 }; 739 enum hl_clk_throttling_type { 740 HL_CLK_THROTTLE_TYPE_POWER, 741 HL_CLK_THROTTLE_TYPE_THERMAL, 742 HL_CLK_THROTTLE_TYPE_MAX 743 }; 744 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) 745 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL) 746 struct hl_info_clk_throttle { 747 __u32 clk_throttling_reason; 748 __u32 pad; 749 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX]; 750 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX]; 751 }; 752 struct hl_info_energy { 753 __u64 total_energy_consumption; 754 }; 755 #define HL_PLL_NUM_OUTPUTS 4 756 struct hl_pll_frequency_info { 757 __u16 output[HL_PLL_NUM_OUTPUTS]; 758 }; 759 struct hl_open_stats_info { 760 __u64 open_counter; 761 __u64 last_open_period_ms; 762 __u8 is_compute_ctx_active; 763 __u8 compute_ctx_in_release; 764 __u8 pad[6]; 765 }; 766 struct hl_power_info { 767 __u64 power; 768 }; 769 struct hl_info_sync_manager { 770 __u32 first_available_sync_object; 771 __u32 first_available_monitor; 772 __u32 first_available_cq; 773 __u32 reserved; 774 }; 775 struct hl_info_cs_counters { 776 __u64 total_out_of_mem_drop_cnt; 777 __u64 ctx_out_of_mem_drop_cnt; 778 __u64 total_parsing_drop_cnt; 779 __u64 ctx_parsing_drop_cnt; 780 __u64 total_queue_full_drop_cnt; 781 __u64 ctx_queue_full_drop_cnt; 782 __u64 total_device_in_reset_drop_cnt; 783 __u64 ctx_device_in_reset_drop_cnt; 784 __u64 total_max_cs_in_flight_drop_cnt; 785 __u64 ctx_max_cs_in_flight_drop_cnt; 786 __u64 total_validation_drop_cnt; 787 __u64 ctx_validation_drop_cnt; 788 }; 789 struct hl_info_last_err_open_dev_time { 790 __s64 timestamp; 791 }; 792 struct hl_info_cs_timeout_event { 793 __s64 timestamp; 794 __u64 seq; 795 }; 796 #define HL_RAZWI_NA_ENG_ID U16_MAX 797 #define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128 798 #define HL_RAZWI_READ BIT(0) 799 #define HL_RAZWI_WRITE BIT(1) 800 #define HL_RAZWI_LBW BIT(2) 801 #define HL_RAZWI_HBW BIT(3) 802 #define HL_RAZWI_RR BIT(4) 803 #define HL_RAZWI_ADDR_DEC BIT(5) 804 struct hl_info_razwi_event { 805 __s64 timestamp; 806 __u64 addr; 807 __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR]; 808 __u16 num_of_possible_engines; 809 __u8 flags; 810 __u8 pad[5]; 811 }; 812 #define MAX_QMAN_STREAMS_INFO 4 813 #define OPCODE_INFO_MAX_ADDR_SIZE 8 814 struct hl_info_undefined_opcode_event { 815 __s64 timestamp; 816 __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE]; 817 __u64 cq_addr; 818 __u32 cq_size; 819 __u32 cb_addr_streams_len; 820 __u32 engine_id; 821 __u32 stream_id; 822 }; 823 struct hl_info_dev_memalloc_page_sizes { 824 __u64 page_order_bitmask; 825 }; 826 #define SEC_PCR_DATA_BUF_SZ 256 827 #define SEC_PCR_QUOTE_BUF_SZ 510 828 #define SEC_SIGNATURE_BUF_SZ 255 829 #define SEC_PUB_DATA_BUF_SZ 510 830 #define SEC_CERTIFICATE_BUF_SZ 2046 831 struct hl_info_sec_attest { 832 __u32 nonce; 833 __u16 pcr_quote_len; 834 __u16 pub_data_len; 835 __u16 certificate_len; 836 __u8 pcr_num_reg; 837 __u8 pcr_reg_len; 838 __u8 quote_sig_len; 839 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 840 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 841 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 842 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 843 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 844 __u8 pad0[2]; 845 }; 846 struct hl_page_fault_info { 847 __s64 timestamp; 848 __u64 addr; 849 __u16 engine_id; 850 __u8 pad[6]; 851 }; 852 struct hl_user_mapping { 853 __u64 dev_va; 854 __u64 size; 855 }; 856 enum gaudi_dcores { 857 HL_GAUDI_WS_DCORE, 858 HL_GAUDI_WN_DCORE, 859 HL_GAUDI_EN_DCORE, 860 HL_GAUDI_ES_DCORE 861 }; 862 struct hl_info_args { 863 __u64 return_pointer; 864 __u32 return_size; 865 __u32 op; 866 union { 867 __u32 dcore_id; 868 __u32 ctx_id; 869 __u32 period_ms; 870 __u32 pll_index; 871 __u32 eventfd; 872 __u32 user_buffer_actual_size; 873 __u32 sec_attest_nonce; 874 __u32 array_size; 875 }; 876 __u32 pad; 877 }; 878 #define HL_CB_OP_CREATE 0 879 #define HL_CB_OP_DESTROY 1 880 #define HL_CB_OP_INFO 2 881 #define HL_MAX_CB_SIZE (0x200000 - 32) 882 #define HL_CB_FLAGS_MAP 0x1 883 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2 884 struct hl_cb_in { 885 __u64 cb_handle; 886 __u32 op; 887 __u32 cb_size; 888 __u32 ctx_id; 889 __u32 flags; 890 }; 891 struct hl_cb_out { 892 union { 893 __u64 cb_handle; 894 union { 895 struct { 896 __u32 usage_cnt; 897 __u32 pad; 898 }; 899 __u64 device_va; 900 }; 901 }; 902 }; 903 union hl_cb_args { 904 struct hl_cb_in in; 905 struct hl_cb_out out; 906 }; 907 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 908 struct hl_cs_chunk { 909 union { 910 __u64 cb_handle; 911 __u64 signal_seq_arr; 912 __u64 encaps_signal_seq; 913 }; 914 __u32 queue_index; 915 union { 916 __u32 cb_size; 917 __u32 num_signal_seq_arr; 918 __u32 encaps_signal_offset; 919 }; 920 __u32 cs_chunk_flags; 921 __u32 collective_engine_id; 922 __u32 pad[10]; 923 }; 924 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 925 #define HL_CS_FLAGS_SIGNAL 0x2 926 #define HL_CS_FLAGS_WAIT 0x4 927 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 928 #define HL_CS_FLAGS_TIMESTAMP 0x20 929 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 930 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 931 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 932 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 933 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 934 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 935 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 936 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 937 #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000 938 #define HL_CS_STATUS_SUCCESS 0 939 #define HL_MAX_JOBS_PER_CS 512 940 #define HL_ENGINE_CORE_HALT (1 << 0) 941 #define HL_ENGINE_CORE_RUN (1 << 1) 942 struct hl_cs_in { 943 union { 944 struct { 945 __u64 chunks_restore; 946 __u64 chunks_execute; 947 }; 948 struct { 949 __u64 engine_cores; 950 __u32 num_engine_cores; 951 __u32 core_command; 952 }; 953 }; 954 union { 955 __u64 seq; 956 __u32 encaps_sig_handle_id; 957 struct { 958 __u32 encaps_signals_count; 959 __u32 encaps_signals_q_idx; 960 }; 961 }; 962 __u32 num_chunks_restore; 963 __u32 num_chunks_execute; 964 __u32 timeout; 965 __u32 cs_flags; 966 __u32 ctx_id; 967 __u8 pad[4]; 968 }; 969 struct hl_cs_out { 970 union { 971 __u64 seq; 972 struct { 973 __u32 handle_id; 974 __u32 count; 975 }; 976 }; 977 __u32 status; 978 __u32 sob_base_addr_offset; 979 __u16 sob_count_before_submission; 980 __u16 pad[3]; 981 }; 982 union hl_cs_args { 983 struct hl_cs_in in; 984 struct hl_cs_out out; 985 }; 986 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 987 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 988 #define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000 989 #define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000 990 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 991 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 992 #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20 993 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 994 struct hl_wait_cs_in { 995 union { 996 struct { 997 __u64 seq; 998 __u64 timeout_us; 999 }; 1000 struct { 1001 union { 1002 __u64 addr; 1003 __u64 cq_counters_handle; 1004 }; 1005 __u64 target; 1006 }; 1007 }; 1008 __u32 ctx_id; 1009 __u32 flags; 1010 union { 1011 struct { 1012 __u8 seq_arr_len; 1013 __u8 pad[7]; 1014 }; 1015 __u64 interrupt_timeout_us; 1016 }; 1017 __u64 cq_counters_offset; 1018 __u64 timestamp_handle; 1019 __u64 timestamp_offset; 1020 }; 1021 #define HL_WAIT_CS_STATUS_COMPLETED 0 1022 #define HL_WAIT_CS_STATUS_BUSY 1 1023 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 1024 #define HL_WAIT_CS_STATUS_ABORTED 3 1025 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 1026 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 1027 struct hl_wait_cs_out { 1028 __u32 status; 1029 __u32 flags; 1030 __s64 timestamp_nsec; 1031 __u32 cs_completion_map; 1032 __u32 pad; 1033 }; 1034 union hl_wait_cs_args { 1035 struct hl_wait_cs_in in; 1036 struct hl_wait_cs_out out; 1037 }; 1038 #define HL_MEM_OP_ALLOC 0 1039 #define HL_MEM_OP_FREE 1 1040 #define HL_MEM_OP_MAP 2 1041 #define HL_MEM_OP_UNMAP 3 1042 #define HL_MEM_OP_MAP_BLOCK 4 1043 #define HL_MEM_OP_EXPORT_DMABUF_FD 5 1044 #define HL_MEM_OP_TS_ALLOC 6 1045 #define HL_MEM_CONTIGUOUS 0x1 1046 #define HL_MEM_SHARED 0x2 1047 #define HL_MEM_USERPTR 0x4 1048 #define HL_MEM_FORCE_HINT 0x8 1049 #define HL_MEM_PREFETCH 0x40 1050 struct hl_mem_in { 1051 union { 1052 struct { 1053 __u64 mem_size; 1054 __u64 page_size; 1055 } alloc; 1056 struct { 1057 __u64 handle; 1058 } free; 1059 struct { 1060 __u64 hint_addr; 1061 __u64 handle; 1062 } map_device; 1063 struct { 1064 __u64 host_virt_addr; 1065 __u64 hint_addr; 1066 __u64 mem_size; 1067 } map_host; 1068 struct { 1069 __u64 block_addr; 1070 } map_block; 1071 struct { 1072 __u64 device_virt_addr; 1073 } unmap; 1074 struct { 1075 __u64 handle; 1076 __u64 mem_size; 1077 } export_dmabuf_fd; 1078 }; 1079 __u32 op; 1080 __u32 flags; 1081 __u32 ctx_id; 1082 __u32 num_of_elements; 1083 }; 1084 struct hl_mem_out { 1085 union { 1086 __u64 device_virt_addr; 1087 __u64 handle; 1088 struct { 1089 __u64 block_handle; 1090 __u32 block_size; 1091 __u32 pad; 1092 }; 1093 __s32 fd; 1094 }; 1095 }; 1096 union hl_mem_args { 1097 struct hl_mem_in in; 1098 struct hl_mem_out out; 1099 }; 1100 #define HL_DEBUG_MAX_AUX_VALUES 10 1101 struct hl_debug_params_etr { 1102 __u64 buffer_address; 1103 __u64 buffer_size; 1104 __u32 sink_mode; 1105 __u32 pad; 1106 }; 1107 struct hl_debug_params_etf { 1108 __u64 buffer_address; 1109 __u64 buffer_size; 1110 __u32 sink_mode; 1111 __u32 pad; 1112 }; 1113 struct hl_debug_params_stm { 1114 __u64 he_mask; 1115 __u64 sp_mask; 1116 __u32 id; 1117 __u32 frequency; 1118 }; 1119 struct hl_debug_params_bmon { 1120 __u64 start_addr0; 1121 __u64 addr_mask0; 1122 __u64 start_addr1; 1123 __u64 addr_mask1; 1124 __u32 bw_win; 1125 __u32 win_capture; 1126 __u32 id; 1127 __u32 control; 1128 __u64 start_addr2; 1129 __u64 end_addr2; 1130 __u64 start_addr3; 1131 __u64 end_addr3; 1132 }; 1133 struct hl_debug_params_spmu { 1134 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 1135 __u32 event_types_num; 1136 __u32 pmtrc_val; 1137 __u32 trc_ctrl_host_val; 1138 __u32 trc_en_host_val; 1139 }; 1140 #define HL_DEBUG_OP_ETR 0 1141 #define HL_DEBUG_OP_ETF 1 1142 #define HL_DEBUG_OP_STM 2 1143 #define HL_DEBUG_OP_FUNNEL 3 1144 #define HL_DEBUG_OP_BMON 4 1145 #define HL_DEBUG_OP_SPMU 5 1146 #define HL_DEBUG_OP_TIMESTAMP 6 1147 #define HL_DEBUG_OP_SET_MODE 7 1148 struct hl_debug_args { 1149 __u64 input_ptr; 1150 __u64 output_ptr; 1151 __u32 input_size; 1152 __u32 output_size; 1153 __u32 op; 1154 __u32 reg_idx; 1155 __u32 enable; 1156 __u32 ctx_id; 1157 }; 1158 #define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args) 1159 #define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args) 1160 #define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args) 1161 #define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args) 1162 #define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args) 1163 #define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args) 1164 #define HL_COMMAND_START 0x01 1165 #define HL_COMMAND_END 0x07 1166 #endif 1167