1 /*
2 * Copyright (c) 2015 Google Inc. All rights reserved
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <debug.h>
25 #include <dev/timer/arm_generic.h>
26 #include <err.h>
27 #include <inttypes.h>
28 #include <kernel/vm.h>
29 #include <lib/device_tree/libfdt_helpers.h>
30 #include <lib/dtb_service/dtb_service.h>
31 #include <lk/init.h>
32 #include <platform/gic.h>
33 #include <string.h>
34 #include <sys/types.h>
35 #if ARM64_BOOT_PROTOCOL_X0_DTB
36 #include <vsock/vsock.h>
37 #if MMIO_GUARD_ENABLED
38 #include <lib/libhypervisor/libhypervisor.h>
39 #endif
40 #endif
41
42 #include "debug.h"
43
44 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
45 #include "smc.h"
46 #endif
47
48 #ifdef GIC_VERSION
49 #include <dev/interrupt/arm_gic.h>
50
51 #define ARM_GENERIC_TIMER_INT_CNTV 27
52 #define ARM_GENERIC_TIMER_INT_CNTPS 29
53 #define ARM_GENERIC_TIMER_INT_CNTP 30
54
55 #define ARM_GENERIC_TIMER_INT_SELECTED(timer) ARM_GENERIC_TIMER_INT_##timer
56 #define XARM_GENERIC_TIMER_INT_SELECTED(timer) \
57 ARM_GENERIC_TIMER_INT_SELECTED(timer)
58 #define ARM_GENERIC_TIMER_INT \
59 XARM_GENERIC_TIMER_INT_SELECTED(TIMER_ARM_GENERIC_SELECTED)
60
61 #if GIC_VERSION <= 2
62 #define GICC_SIZE (0x1000)
63 #define GICD_SIZE (0x1000)
64 #define GICR_SIZE (0)
65 #else
66 #define GICC_SIZE (0x10000)
67 #define GICD_SIZE (0x10000)
68 #if GIC_VERSION < 4
69 #define GICR_SIZE (0x20000 * SMP_MAX_CPUS)
70 #else
71 #define GICR_SIZE (0x40000 * SMP_MAX_CPUS)
72 #endif
73 #endif
74 #elif HAFNIUM
75 #include <hf/types.h>
76 #define ARM_GENERIC_TIMER_INT HF_VIRTUAL_TIMER_INTID
77 #else
78 #error "Unknown interrupt library"
79 #endif
80
81 extern ulong lk_boot_args[4];
82
83 #if ARM64_BOOT_PROTOCOL_X0_DTB
generic_arm64_reserve_device_tree(paddr_t ram_base,size_t ram_size)84 static void generic_arm64_reserve_device_tree(paddr_t ram_base,
85 size_t ram_size) {
86 struct list_node list;
87 list_initialize(&list);
88
89 paddr_t fdt_paddr = lk_boot_args[0];
90 if (fdt_paddr < ram_base || fdt_paddr - ram_base >= ram_size) {
91 /* fdt address is outside ram_arena, no need to reserve it */
92 return;
93 }
94 const void* fdt = paddr_to_kvaddr(fdt_paddr);
95 if (fdt_check_header(fdt)) {
96 return;
97 }
98 size_t fdt_size = fdt_totalsize(fdt);
99 /* if fdt_paddr is not page aligned add offset in first page to size */
100 fdt_size += fdt_paddr & (PAGE_SIZE - 1);
101 uint fdt_page_count = DIV_ROUND_UP(fdt_size, PAGE_SIZE);
102 uint fdt_reserved_page_count =
103 pmm_alloc_range(fdt_paddr, fdt_page_count, &list);
104 if (fdt_page_count != fdt_reserved_page_count) {
105 panic("failed to reserve memory for device tree");
106 }
107 }
108 #endif
109
110 /* initial memory mappings. parsed by start.S */
111 struct mmu_initial_mapping mmu_initial_mappings[] = {
112 /* Mark next entry as dynamic as it might be updated
113 by platform_reset code to specify actual size and
114 location of RAM to use */
115 {.phys = MEMBASE + KERNEL_LOAD_OFFSET,
116 .virt = KERNEL_BASE + KERNEL_LOAD_OFFSET,
117 .size = MEMSIZE,
118 .flags = MMU_INITIAL_MAPPING_FLAG_DYNAMIC,
119 .name = "ram"},
120
121 /* null entry to terminate the list */
122 {0, 0, 0, 0, 0}};
123
124 static pmm_arena_t ram_arena = {.name = "ram",
125 .base = MEMBASE + KERNEL_LOAD_OFFSET,
126 .size = MEMSIZE,
127 .flags = PMM_ARENA_FLAG_KMAP};
128
platform_init_mmu_mappings(void)129 void platform_init_mmu_mappings(void) {
130 /* go through mmu_initial_mapping to find dynamic entry
131 * matching ram_arena (by name) and adjust it.
132 */
133 struct mmu_initial_mapping* m = mmu_initial_mappings;
134 for (uint i = 0; i < countof(mmu_initial_mappings); i++, m++) {
135 if (!(m->flags & MMU_INITIAL_MAPPING_FLAG_DYNAMIC))
136 continue;
137
138 if (strcmp(m->name, ram_arena.name) == 0) {
139 /* update ram_arena */
140 ram_arena.base = m->phys;
141 ram_arena.size = m->size;
142 ram_arena.flags = PMM_ARENA_FLAG_KMAP;
143
144 break;
145 }
146 }
147 pmm_add_arena(&ram_arena);
148 #if ARM64_BOOT_PROTOCOL_X0_DTB
149 generic_arm64_reserve_device_tree(ram_arena.base, ram_arena.size);
150 #endif
151 }
152
153 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
154
generic_arm64_get_reg_base(int reg)155 static paddr_t generic_arm64_get_reg_base(int reg) {
156 #if ARCH_ARM64
157 return generic_arm64_smc(SMC_FC64_GET_REG_BASE, reg, 0, 0);
158 #else
159 return generic_arm64_smc(SMC_FC_GET_REG_BASE, reg, 0, 0);
160 #endif
161 }
162
163 #endif
164
165 #if ARM64_BOOT_PROTOCOL_X0_DTB
pci_init_fdt(const void * fdt)166 int static pci_init_fdt(const void* fdt) {
167 int fdt_pci_offset =
168 fdt_node_offset_by_compatible(fdt, 0, "pci-host-cam-generic");
169 if (fdt_pci_offset < 0) {
170 dprintf(CRITICAL, "failed to find pci device tree node\n");
171 return ERR_NOT_FOUND;
172 }
173
174 paddr_t pci_paddr;
175 size_t pci_size;
176 int ret = fdt_helper_get_reg(fdt, fdt_pci_offset, 0, &pci_paddr, &pci_size);
177 if (ret) {
178 dprintf(CRITICAL, "failed to find get reg, err %d\n", ret);
179 return ERR_NOT_VALID;
180 }
181
182 return pci_init_mmio(pci_paddr, pci_size, 1 << 11);
183 }
184 #endif /* ARM64_BOOT_PROTOCOL_X0_DTB */
185
platform_after_vm_init(uint level)186 static void platform_after_vm_init(uint level) {
187 #ifdef GIC_VERSION
188 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
189 paddr_t gicc = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICC);
190 paddr_t gicd = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICD);
191 paddr_t gicr = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICR);
192 #elif ARM64_BOOT_PROTOCOL_X0_DTB
193 int ret;
194 void* fdt_temp;
195 size_t fdt_size;
196 paddr_t fdt_paddr = lk_boot_args[0];
197 ret = vmm_alloc_physical(vmm_get_kernel_aspace(), "device_tree_probe",
198 PAGE_SIZE, &fdt_temp, 0, fdt_paddr, 0,
199 ARCH_MMU_FLAG_PERM_NO_EXECUTE |
200 ARCH_MMU_FLAG_CACHED |
201 ARCH_MMU_FLAG_PERM_RO);
202 if (ret) {
203 dprintf(CRITICAL,
204 "failed to map device tree page at 0x%" PRIxPADDR ": %d\n",
205 fdt_paddr, ret);
206 return;
207 }
208 const void* fdt = fdt_temp;
209
210 if (fdt_check_header(fdt)) {
211 dprintf(CRITICAL, "invalid device tree at 0x%" PRIxPADDR ": %d\n",
212 fdt_paddr, ret);
213 return;
214 }
215
216 fdt_size = fdt_totalsize(fdt);
217 if (fdt_size > PAGE_SIZE) {
218 fdt_size = page_align(fdt_size);
219 dprintf(INFO, "remapping device tree with size 0x%zx\n", fdt_size);
220 vmm_free_region(vmm_get_kernel_aspace(), (vaddr_t)fdt);
221 ret = vmm_alloc_physical(vmm_get_kernel_aspace(), "device_tree_full",
222 fdt_size, &fdt_temp, 0, fdt_paddr, 0,
223 ARCH_MMU_FLAG_PERM_NO_EXECUTE |
224 ARCH_MMU_FLAG_CACHED |
225 ARCH_MMU_FLAG_PERM_RO);
226 fdt = fdt_temp;
227 if (ret) {
228 dprintf(CRITICAL,
229 "failed to map device tree at 0x%" PRIxPADDR
230 " sz 0x%zx: %d\n",
231 fdt_paddr, fdt_size, ret);
232 return;
233 }
234 }
235
236 generic_arm64_setup_uart(fdt);
237
238 int fdt_gic_offset = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
239 paddr_t gicc = 0; /* gic-v3 does not need a memory mapped gicc */
240 paddr_t gicd, gicr;
241 size_t gicd_size, gicr_size;
242 if (fdt_helper_get_reg(fdt, fdt_gic_offset, 0, &gicd, &gicd_size)) {
243 dprintf(CRITICAL, "failed get gicd regs, offset %d\n", fdt_gic_offset);
244 return;
245 }
246 if (fdt_helper_get_reg(fdt, fdt_gic_offset, 1, &gicr, &gicr_size)) {
247 dprintf(CRITICAL, "failed get gicr regs, offset %d\n", fdt_gic_offset);
248 return;
249 }
250 if (gicd_size != GICD_SIZE) {
251 dprintf(CRITICAL, "unexpected gicd_size %zd != %d\n", gicd_size,
252 GICD_SIZE);
253 return;
254 }
255 if (gicr_size < GICR_SIZE) {
256 dprintf(CRITICAL, "unexpected gicr_size %zd < %d\n", gicr_size,
257 GICR_SIZE);
258 return;
259 }
260
261 #if MMIO_GUARD_ENABLED
262 /*
263 * MMIO Guard map GIC addresses. Ignore not supported which implies that
264 * guard is not used.
265 */
266 ret = hypervisor_mmio_map_region(gicc, GICC_SIZE);
267 if (ret != NO_ERROR && ret != ERR_NOT_SUPPORTED) {
268 dprintf(CRITICAL, "failed to mmio guard map gicc. error=%d\n", ret);
269 }
270 ret = hypervisor_mmio_map_region(gicd, GICD_SIZE);
271 if (ret != NO_ERROR && ret != ERR_NOT_SUPPORTED) {
272 dprintf(CRITICAL, "failed to mmio guard map gicd. error=%d\n", ret);
273 }
274 ret = hypervisor_mmio_map_region(gicr, GICR_SIZE);
275 if (ret != NO_ERROR && ret != ERR_NOT_SUPPORTED) {
276 dprintf(CRITICAL, "failed to mmio guard map gicr. error=%d\n", ret);
277 }
278 #endif
279 #else
280 #error "Unknown ARM64_BOOT_PROTOCOL"
281 #endif
282 dprintf(SPEW,
283 "gicc 0x%" PRIxPADDR ", gicd 0x%" PRIxPADDR ", gicr 0x%" PRIxPADDR
284 "\n",
285 gicc, gicd, gicr);
286
287 /* initialize the interrupt controller */
288 struct arm_gic_init_info init_info = {
289 .gicc_paddr = gicc,
290 .gicc_size = GICC_SIZE,
291 .gicd_paddr = gicd,
292 .gicd_size = GICD_SIZE,
293 .gicr_paddr = gicr,
294 .gicr_size = GICR_SIZE,
295 };
296 arm_gic_init_map(&init_info);
297 #endif /* GIC_VERSION */
298
299 /* initialize the timer block */
300 arm_generic_timer_init(ARM_GENERIC_TIMER_INT, 0);
301
302 #if ARM64_BOOT_PROTOCOL_X0_DTB
303 if (dtb_set(fdt, fdt_size) != NO_ERROR) {
304 dprintf(CRITICAL, "failed to set device tree\n");
305 }
306 pci_init_fdt(fdt); /* ignore pci init errors */
307 #endif
308 }
309
310 LK_INIT_HOOK(platform_after_vm, platform_after_vm_init, LK_INIT_LEVEL_VM + 1);
311