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Searched refs:operands (Results 1 – 9 of 9) sorted by relevance

/dalvik/vm/compiler/codegen/arm/
DLocalOptimizations.c26 return ((lir->operands[1] == rFP) && in isDalvikLoad()
35 return ((lir->operands[1] == rFP) && in isDalvikStore()
62 int dRegId = thisLIR->operands[2]; in applyLoadStoreElimination()
63 int nativeRegId = thisLIR->operands[0]; in applyLoadStoreElimination()
73 checkLIR->operands[2] == dRegId ) { in applyLoadStoreElimination()
74 if (FPREG(nativeRegId) != FPREG(checkLIR->operands[0])) { in applyLoadStoreElimination()
78 if (checkLIR->operands[0] != nativeRegId) { in applyLoadStoreElimination()
81 checkLIR->operands[0], in applyLoadStoreElimination()
95 checkLIR->operands[2] == dRegId) { in applyLoadStoreElimination()
122 checkLIR->operands[0] == nativeRegId; in applyLoadStoreElimination()
DArchUtility.c83 operand = lir->operands[nc-'0']; in buildInsnString()
148 int offset_1 = lir->operands[0]; in buildInsnString()
149 int offset_2 = NEXT_LIR(lir)->operands[0]; in buildInsnString()
192 int dest = lir->operands[0]; in dumpLIRInsn()
214 getOpcodeName(lir->operands[1])); in dumpLIRInsn()
221 lir->operands[1]); in dumpLIRInsn()
262 armLIR->operands[0]); in dvmCompilerCodegenDump()
DAssemble.c42 operands, name, fmt, size) \ argument
44 opcode, operands, name, fmt, size}
506 *dataPtr++ = dataLIR->operands[0]; in installDataContent()
532 (lir->operands[0] == 1)) { in assembleInstructions()
551 intptr_t target = lirTarget->generic.offset + lir->operands[2]; in assembleInstructions()
560 lir->operands[1] = delta >> 2; in assembleInstructions()
569 lir->operands[1] = delta >> 1; in assembleInstructions()
578 lir->operands[0] = delta >> 1; in assembleInstructions()
588 lir->operands[0] = delta >> 1; in assembleInstructions()
593 intptr_t target = lir->operands[1]; in assembleInstructions()
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DThumbUtil.c140 res->operands[0] = rDest; in dvmCompilerRegCopy()
141 res->operands[1] = rSrc; in dvmCompilerRegCopy()
172 loadPcRel->operands[0] = rDest; in loadConstant()
179 if (dataTarget->operands[0] != value) { in loadConstant()
180 newLIR2(cUnit, THUMB_ADD_RI8, rDest, value - dataTarget->operands[0]); in loadConstant()
DThumb2Util.c139 res->operands[0] = rDest; in dvmCompilerRegCopy()
140 res->operands[1] = rSrc; in dvmCompilerRegCopy()
252 loadPcRel->operands[0] = rDest; in loadConstant()
259 if (dataTarget->operands[0] != value) { in loadConstant()
260 newLIR2(cUnit, THUMB_ADD_RI8, rDest, value - dataTarget->operands[0]); in loadConstant()
DCodegen.c55 insn->operands[0] = dest; in newLIR1()
67 insn->operands[0] = dest; in newLIR2()
68 insn->operands[1] = src1; in newLIR2()
80 insn->operands[0] = dest; in newLIR3()
81 insn->operands[1] = src1; in newLIR3()
82 insn->operands[2] = src2; in newLIR3()
110 newValue->operands[0] = value; in addWordData()
131 if (((unsigned) (value - ((ArmLIR *) dataTarget)->operands[0])) <= in scanLiteralPool()
152 pcrLabel->operands[0] = dPC; in genReturnCommon()
153 pcrLabel->operands[1] = mir->offset; in genReturnCommon()
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DArmLIR.h357 int operands[3]; // [0..2] = [dest, src1, src2] member
/dalvik/dx/src/com/android/dx/ssa/
DPhiInsn.java44 private final ArrayList<Operand> operands = new ArrayList<Operand>(); field in PhiInsn
90 for (Operand o : operands) { in updateSourcesToDefinitions()
129 operands.add(new Operand(registerSpec, predBlock.getIndex(), in addPhiOperand()
144 return operands.get(sourcesIndex).blockIndex; in predBlockIndexForSourcesIndex()
188 if (operands.size() == 0) { in getSources()
193 int szSources = operands.size(); in getSources()
197 Operand o = operands.get(i); in getSources()
214 for (Operand o : operands) { in isRegASource()
227 if (operands.size() == 0 ) { in areAllOperandsEqual()
232 int firstReg = operands.get(0).regSpec.getReg(); in areAllOperandsEqual()
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/dalvik/vm/compiler/template/out/
DCompilerTemplateAsm-armv5te.S436 * on what value we'd like to return when one of the operands is NaN.
481 * on what value we'd like to return when one of the operands is NaN.
526 * on what value we'd like to return when one of the operands is NaN.