1 /*
2 * Copyright (C) 2009 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "../../CompilerInternals.h"
18 #include "dexdump/OpCodeNames.h"
19 #include "ArmLIR.h"
20
21 /* Decode and print a ARM register name */
decodeRegList(int vector,char * buf)22 static char * decodeRegList(int vector, char *buf)
23 {
24 int i;
25 bool printed = false;
26 buf[0] = 0;
27 for (i = 0; i < 8; i++, vector >>= 1) {
28 if (vector & 0x1) {
29 if (printed) {
30 sprintf(buf + strlen(buf), ", r%d", i);
31 } else {
32 printed = true;
33 sprintf(buf, "r%d", i);
34 }
35 }
36 }
37 return buf;
38 }
39
expandImmediate(int value)40 static int expandImmediate(int value)
41 {
42 int mode = (value & 0xf00) >> 8;
43 u4 bits = value & 0xff;
44 switch(mode) {
45 case 0:
46 return bits;
47 case 1:
48 return (bits << 16) | bits;
49 case 2:
50 return (bits << 24) | (bits << 8);
51 case 3:
52 return (bits << 24) | (bits << 16) | (bits << 8) | bits;
53 default:
54 break;
55 }
56 bits = (bits | 0x80) << 24;
57 return bits >> (((value & 0xf80) >> 7) - 8);
58 }
59
60 /*
61 * Interpret a format string and build a string no longer than size
62 * See format key in Assemble.c.
63 */
buildInsnString(char * fmt,ArmLIR * lir,char * buf,unsigned char * baseAddr,int size)64 static void buildInsnString(char *fmt, ArmLIR *lir, char* buf,
65 unsigned char *baseAddr, int size)
66 {
67 int i;
68 char *bufEnd = &buf[size-1];
69 char *fmtEnd = &fmt[strlen(fmt)];
70 char tbuf[256];
71 char nc;
72 while (fmt < fmtEnd) {
73 int operand;
74 if (*fmt == '!') {
75 fmt++;
76 assert(fmt < fmtEnd);
77 nc = *fmt++;
78 if (nc=='!') {
79 strcpy(tbuf, "!");
80 } else {
81 assert(fmt < fmtEnd);
82 assert((unsigned)(nc-'0') < 3);
83 operand = lir->operands[nc-'0'];
84 switch(*fmt++) {
85 case 'm':
86 operand = expandImmediate(operand);
87 sprintf(tbuf,"%d [0x%x]", operand, operand);
88 break;
89 case 's':
90 sprintf(tbuf,"s%d",operand & FP_REG_MASK);
91 break;
92 case 'S':
93 sprintf(tbuf,"d%d",(operand & FP_REG_MASK) >> 1);
94 break;
95 case 'h':
96 sprintf(tbuf,"%04x", operand);
97 break;
98 case 'M':
99 case 'd':
100 sprintf(tbuf,"%d", operand);
101 break;
102 case 'D':
103 sprintf(tbuf,"%d", operand+8);
104 break;
105 case 'E':
106 sprintf(tbuf,"%d", operand*4);
107 break;
108 case 'F':
109 sprintf(tbuf,"%d", operand*2);
110 break;
111 case 'c':
112 switch (operand) {
113 case ARM_COND_EQ:
114 strcpy(tbuf, "beq");
115 break;
116 case ARM_COND_NE:
117 strcpy(tbuf, "bne");
118 break;
119 case ARM_COND_LT:
120 strcpy(tbuf, "blt");
121 break;
122 case ARM_COND_GE:
123 strcpy(tbuf, "bge");
124 break;
125 case ARM_COND_GT:
126 strcpy(tbuf, "bgt");
127 break;
128 case ARM_COND_LE:
129 strcpy(tbuf, "ble");
130 break;
131 case ARM_COND_CS:
132 strcpy(tbuf, "bcs");
133 break;
134 case ARM_COND_MI:
135 strcpy(tbuf, "bmi");
136 break;
137 default:
138 strcpy(tbuf, "");
139 break;
140 }
141 break;
142 case 't':
143 sprintf(tbuf,"0x%08x",
144 (int) baseAddr + lir->generic.offset + 4 +
145 (operand << 1));
146 break;
147 case 'u': {
148 int offset_1 = lir->operands[0];
149 int offset_2 = NEXT_LIR(lir)->operands[0];
150 intptr_t target =
151 ((((intptr_t) baseAddr + lir->generic.offset + 4) &
152 ~3) + (offset_1 << 21 >> 9) + (offset_2 << 1)) &
153 0xfffffffc;
154 sprintf(tbuf, "%p", (void *) target);
155 break;
156 }
157
158 /* Nothing to print for BLX_2 */
159 case 'v':
160 strcpy(tbuf, "see above");
161 break;
162 case 'R':
163 decodeRegList(operand, tbuf);
164 break;
165 default:
166 strcpy(tbuf,"DecodeError");
167 break;
168 }
169 if (buf+strlen(tbuf) <= bufEnd) {
170 strcpy(buf, tbuf);
171 buf += strlen(tbuf);
172 } else {
173 break;
174 }
175 }
176 } else {
177 *buf++ = *fmt++;
178 }
179 if (buf == bufEnd)
180 break;
181 }
182 *buf = 0;
183 }
184
185 /* Pretty-print a LIR instruction */
dumpLIRInsn(LIR * arg,unsigned char * baseAddr)186 static void dumpLIRInsn(LIR *arg, unsigned char *baseAddr)
187 {
188 ArmLIR *lir = (ArmLIR *) arg;
189 char buf[256];
190 char opName[256];
191 int offset = lir->generic.offset;
192 int dest = lir->operands[0];
193 u2 *cPtr = (u2*)baseAddr;
194 /* Handle pseudo-ops individually, and all regular insns as a group */
195 switch(lir->opCode) {
196 case ARM_PSEUDO_TARGET_LABEL:
197 break;
198 case ARM_PSEUDO_CHAINING_CELL_NORMAL:
199 LOGD("-------- chaining cell (normal): 0x%04x\n", dest);
200 break;
201 case ARM_PSEUDO_CHAINING_CELL_HOT:
202 LOGD("-------- chaining cell (hot): 0x%04x\n", dest);
203 break;
204 case ARM_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED:
205 LOGD("-------- chaining cell (predicted)\n");
206 break;
207 case ARM_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON:
208 LOGD("-------- chaining cell (invoke singleton): %s/%p\n",
209 ((Method *)dest)->name,
210 ((Method *)dest)->insns);
211 break;
212 case ARM_PSEUDO_DALVIK_BYTECODE_BOUNDARY:
213 LOGD("-------- dalvik offset: 0x%04x @ %s\n", dest,
214 getOpcodeName(lir->operands[1]));
215 break;
216 case ARM_PSEUDO_ALIGN4:
217 LOGD("%p (%04x): .align4\n", baseAddr + offset, offset);
218 break;
219 case ARM_PSEUDO_PC_RECONSTRUCTION_CELL:
220 LOGD("-------- reconstruct dalvik PC : 0x%04x @ +0x%04x\n", dest,
221 lir->operands[1]);
222 break;
223 case ARM_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL:
224 /* Do nothing */
225 break;
226 case ARM_PSEUDO_EH_BLOCK_LABEL:
227 LOGD("Exception_Handling:\n");
228 break;
229 case ARM_PSEUDO_NORMAL_BLOCK_LABEL:
230 LOGD("L%#06x:\n", dest);
231 break;
232 default:
233 if (lir->isNop) {
234 break;
235 }
236 buildInsnString(EncodingMap[lir->opCode].name, lir, opName,
237 baseAddr, 256);
238 buildInsnString(EncodingMap[lir->opCode].fmt, lir, buf, baseAddr,
239 256);
240 LOGD("%p (%04x): %-8s%s\n",
241 baseAddr + offset, offset, opName, buf);
242 break;
243 }
244 }
245
246 /* Dump instructions and constant pool contents */
dvmCompilerCodegenDump(CompilationUnit * cUnit)247 void dvmCompilerCodegenDump(CompilationUnit *cUnit)
248 {
249 LOGD("Dumping LIR insns\n");
250 LIR *lirInsn;
251 ArmLIR *armLIR;
252
253 LOGD("installed code is at %p\n", cUnit->baseAddr);
254 LOGD("total size is %d bytes\n", cUnit->totalSize);
255 for (lirInsn = cUnit->firstLIRInsn; lirInsn; lirInsn = lirInsn->next) {
256 dumpLIRInsn(lirInsn, cUnit->baseAddr);
257 }
258 for (lirInsn = cUnit->wordList; lirInsn; lirInsn = lirInsn->next) {
259 armLIR = (ArmLIR *) lirInsn;
260 LOGD("%p (%04x): .word (0x%x)\n",
261 (char*)cUnit->baseAddr + armLIR->generic.offset, armLIR->generic.offset,
262 armLIR->operands[0]);
263 }
264 }
265