Home
last modified time | relevance | path

Searched refs:uint32 (Results 1 – 25 of 67) sorted by relevance

123

/hardware/broadcom/wlan/bcm4329/src/include/
Dbcmpcispi.h64 uint32 spih_ctrl; /* 0x00 SPI Control Register */
65 uint32 spih_stat; /* 0x04 SPI Status Register */
66 uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
67 uint32 spih_ext; /* 0x0C SPI Extension Register */
68 uint32 PAD[4]; /* 0x10-0x1F PADDING */
70 uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
71 uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
72 uint32 PAD[6]; /* 0x28-0x3F PADDING */
74 uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
75 uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
[all …]
Daidmp.h118 uint32 oobselina30;
119 uint32 oobselina74;
120 uint32 PAD[6];
121 uint32 oobselinb30;
122 uint32 oobselinb74;
123 uint32 PAD[6];
124 uint32 oobselinc30;
125 uint32 oobselinc74;
126 uint32 PAD[6];
127 uint32 oobselind30;
[all …]
Dwlioctl.h48 uint32 packetId;
76 uint32 cnt_rxundec;
77 uint32 cnt_rxframe;
95 uint32 version;
96 uint32 length;
113 uint32 nbss_cap;
115 uint32 reserved32[1];
121 uint32 ie_length;
127 uint32 SSID_len;
167 uint32 version;
[all …]
Dsbhnddma.h39 uint32 control;
40 uint32 addr;
41 uint32 ptr;
42 uint32 status;
51 uint32 fifoaddr;
52 uint32 fifodatalow;
53 uint32 fifodatahigh;
54 uint32 pad;
59 uint32 ctrl;
60 uint32 addr;
[all …]
Dsiutils.h41 uint32 cccaps;
43 uint32 pmucaps;
50 uint32 chipst;
113 typedef void (*gpio_handler_t)(uint32 stat, void *arg);
135 extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val);
136 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
137 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
138 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
146 extern uint32 si_addrspace(si_t *sih, uint asidx);
147 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
[all …]
Dsbchipc.h45 uint32 chipid;
46 uint32 capabilities;
47 uint32 corecontrol;
48 uint32 bist;
51 uint32 otpstatus;
52 uint32 otpcontrol;
53 uint32 otpprog;
54 uint32 PAD;
57 uint32 intstatus;
58 uint32 intmask;
[all …]
Dsbsdpcmdev.h40 uint32 PAD[2];
42 uint32 PAD[2];
49 uint32 PAD[92];
56 uint32 PAD[108];
63 uint32 PAD[116];
68 uint32 corecontrol; /* CoreControl, 0x000, rev8 */
69 uint32 corestatus; /* CoreStatus, 0x004, rev8 */
70 uint32 PAD[1];
71 uint32 biststatus; /* BistStatus, 0x00c, rev8 */
84 uint32 intstatus; /* IntStatus, 0x020, rev8 */
[all …]
Dsbconfig.h81 uint32 PAD[2];
82 uint32 sbipsflag;
83 uint32 PAD[3];
84 uint32 sbtpsflag;
85 uint32 PAD[11];
86 uint32 sbtmerrloga;
87 uint32 PAD;
88 uint32 sbtmerrlog;
89 uint32 PAD[3];
90 uint32 sbadmatch3;
[all …]
Dsbsocram.h42 uint32 coreinfo;
43 uint32 bwalloc;
44 uint32 extracoreinfo;
45 uint32 biststat;
46 uint32 bankidx;
47 uint32 standbyctrl;
49 uint32 errlogstatus;
50 uint32 errlogaddr;
52 uint32 cambankidx;
53 uint32 cambankstandbyctrl;
[all …]
Dbcmsdpcm.h163 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
164 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
165 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
166 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
167 uint32 abort; /* AbortCount, SDIO: aborts */
168 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
169 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
170 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
171 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
172 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
[all …]
Dbcmendian.h43 ((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
44 (((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
45 (((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
46 (((uint32)(val) & (uint32)0xff000000U) >> 24)))
50 ((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
51 (((uint32)(val) & (uint32)0xffff0000U) >> 16)))
60 static INLINE uint32
61 bcmswap32(uint32 val) in bcmswap32()
66 static INLINE uint32
67 bcmswap32by16(uint32 val) in bcmswap32by16()
[all …]
Dbcmsdh.h87 extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
88 extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data, int *err);
91 extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err);
92 extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err);
108 extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size);
109 extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data);
127 extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
130 extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
149 extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes);
199 extern uint32 bcmsdh_get_dstatus(void *sdh);
[all …]
Dbcmsdspi.h59 uint32 caps; /* cached value of capabilities reg */
70 uint32 target_dev; /* Target device ID */
71 uint32 intmask; /* Current active interrupts */
74 uint32 controller_type; /* Host controller type */
77 uint32 intrcount; /* Client interrupts */
78 uint32 local_intrcount; /* Controller interrupts */
92 uint32 data_xfer_count; /* Current register transfer size */
93 uint32 cmd53_wr_data; /* Used to pass CMD53 write data */
94 uint32 card_response; /* Used to pass back response status byte */
95 uint32 card_rsp_data; /* Used to pass back response data word */
[all …]
Dbcmutils.h462 uint32 bit;
481 static INLINE uint32
488 store32_ua(uint8 *a, uint32 v) in store32_ua()
511 static INLINE uint32
518 store32_ua(uint8 *a, uint32 v) in store32_ua()
553 ((uint32 *)dst)[0] = ((uint32 *)src1)[0] ^ ((uint32 *)src2)[0]; in xor_128bit_block()
554 ((uint32 *)dst)[1] = ((uint32 *)src1)[1] ^ ((uint32 *)src2)[1]; in xor_128bit_block()
555 ((uint32 *)dst)[2] = ((uint32 *)src1)[2] ^ ((uint32 *)src2)[2]; in xor_128bit_block()
556 ((uint32 *)dst)[3] = ((uint32 *)src1)[3] ^ ((uint32 *)src2)[3]; in xor_128bit_block()
569 extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
[all …]
Dtrxhdr.h38 uint32 magic; /* "HDR0" */
39 uint32 len; /* Length of file including header */
40 uint32 crc32; /* 32-bit CRC from flag_version to end of file */
41 uint32 flag_version; /* 0:15 flags, 16:31 version */
42 uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
/hardware/broadcom/wlan/bcm4329/src/shared/
Dsiutils_priv.h37 typedef uint32 (*si_intrsoff_t)(void *intr_arg);
38 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
45 uint32 event;
54 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
55 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
56 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
57 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
58 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
59 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
61 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
[all …]
Daiutils.c39 STATIC uint32
40 get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
41 uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh);
46 static uint32
47 get_erom_ent(si_t *sih, uint32 *eromptr, uint32 mask, uint32 match) in get_erom_ent()
49 uint32 ent; in get_erom_ent()
53 ent = R_REG(si_osh(sih), (uint32 *)(uintptr)(*eromptr)); in get_erom_ent()
54 *eromptr += sizeof(uint32); in get_erom_ent()
79 STATIC uint32
80 get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st, in get_asd()
[all …]
Dsbutils.c42 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
43 static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
45 static uint32 _sb_coresba(si_info_t *sii);
61 static uint32
62 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr) in sb_read_sbreg()
65 uint32 val, intr_val = 0; in sb_read_sbreg()
78 sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */ in sb_read_sbreg()
93 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v) in sb_write_sbreg()
96 volatile uint32 dummy; in sb_write_sbreg()
97 uint32 intr_val = 0; in sb_write_sbreg()
[all …]
Dsiutils.c53 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
58 static uint32 si_gpioreservation = 0;
99 static uint32 wd_msticks; /* watchdog timer ticks normalized to ms */
184 si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin, in si_buscore_setup()
296 uint32 w, savewin; in si_doattach()
327 savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32)); in si_doattach()
500 return R_REG(sii->osh, ((uint32 *)(uintptr) in si_intflag()
731 uint32
744 uint32
757 uint32
[all …]
/hardware/broadcom/wlan/bcm4329/src/include/proto/
D802.11e.h62 uint32 min_srv_interval; /* Minimum Service Interval (us) */
63 uint32 max_srv_interval; /* Maximum Service Interval (us) */
64 uint32 inactivity_interval; /* Inactivity Interval (us) */
65 uint32 suspension_interval; /* Suspension Interval (us) */
66 uint32 srv_start_time; /* Service Start Time (us) */
67 uint32 min_data_rate; /* Minimum Data Rate (bps) */
68 uint32 mean_data_rate; /* Mean Data Rate (bps) */
69 uint32 peak_data_rate; /* Peak Data Rate (bps) */
70 uint32 max_burst_size; /* Maximum Burst Size (bytes) */
71 uint32 delay_bound; /* Delay Bound (us) */
[all …]
/hardware/ti/omap3/omx/ti_omx_config_parser/src/
Dti_video_config_parser.cpp29 (dw) = ((uint32) *(pb + 3) << 24) + \
30 ((uint32) *(pb + 2) << 16) + \
34 #define GetUnalignedDwordEx( pb, dw ) GetUnalignedDword( pb, dw ); (pb) += sizeof(uint32);
45 ((uint32)(uint8)(ch0) | ((uint32)(uint8)(ch1) << 8) | \
46 ((uint32)(uint8)(ch2) << 16) | ((uint32)(uint8)(ch3) << 24 ))
90 aOutputs->width = (uint32)display_width; in ti_video_config_parser()
91 aOutputs->height = (uint32)display_height; in ti_video_config_parser()
92 aOutputs->profile = (uint32)profile_level; // for mp4, profile/level info is packed in ti_video_config_parser()
157 aOutputs->width = (uint32)display_width; in ti_video_config_parser()
158 aOutputs->height = (uint32)display_height; in ti_video_config_parser()
[all …]
/hardware/msm7k/librpc/rpc/
Dtypes.h84 typedef uint32_t uint32; typedef
281 uint32 low;
282 uint32 high;
297 uint32 low;
298 uint32 high;
325 uint32 padding;
367 bool_t (*send_uint32) (xdr_s_type *xdr, const uint32 *value);
368 bool_t (*send_bytes) (xdr_s_type *xdr, const uint8 *buf, uint32 len);
375 bool_t (*recv_uint32) (xdr_s_type *xdr, uint32 *value);
376 bool_t (*recv_bytes) (xdr_s_type *xdr, uint8 *buf, uint32 len);
[all …]
/hardware/broadcom/wlan/bcm4329/src/bcmsdio/sys/
Dbcmsdspi.c67 static void sdspi_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count);
68 static int sdspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd, uint32 arg,
69 uint32 *data, uint32 datalen);
70 static int sdspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
71 int regsize, uint32 *data);
72 static int sdspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
73 int regsize, uint32 data);
77 uint32 addr, int nbytes, uint32 *data);
82 static uint8 sdspi_crc7(unsigned char* p, uint32 len);
83 static uint16 sdspi_crc16(unsigned char* p, uint32 len);
[all …]
Dbcmsdh.c50 uint32 vendevid; /* Target Vendor and Device ID on SD bus */
53 uint32 sbwad; /* Save backplane window address */
93 *regsva = (uint32 *)SI_ENUM_BASE; in bcmsdh_attach()
206 bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err) in bcmsdh_cfg_read()
228 bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, uint8 data, int *err) in bcmsdh_cfg_write()
246 uint32
247 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err) in bcmsdh_cfg_read_word()
251 uint32 data = 0; in bcmsdh_cfg_read_word()
271 bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err) in bcmsdh_cfg_write_word()
332 bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address) in bcmsdhsdio_set_sbaddr_window()
[all …]
/hardware/msm7k/librpc/
Dsvc_clnt_common.c8 extern int r_read(int handle, char *buf, uint32 size);
9 extern int r_write(int handle, const char *buf, uint32 size);
10 extern int r_control(int handle, const uint32 cmd, void *arg);
65 xdr->out_next = (RPC_OFFSET+2)*sizeof(uint32); in xdr_std_msg_start()
68 ((uint32 *)xdr->out_msg)[RPC_OFFSET] = htonl(xdr->xid); in xdr_std_msg_start()
70 ((uint32 *)xdr->out_msg)[RPC_OFFSET+1] = htonl(rpc_msg_type); in xdr_std_msg_start()
112 static bool_t xdr_std_send_uint32(xdr_s_type *xdr, const uint32 *value) in xdr_std_send_uint32()
122 uint32 val = *value; in xdr_std_send_int8()
128 uint32 val = *value; in xdr_std_send_uint8()
134 uint32 val = *value; in xdr_std_send_int16()
[all …]

123