1 /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
2
3 #define LINUX_OUT_MACROS
4
5 #include "etherboot.h"
6 #include "nic.h"
7 #include "cards.h"
8 #include "timer.h"
9 #include "epic100.h"
10
11 #undef virt_to_bus
12 #define virt_to_bus(x) ((unsigned long)x)
13
14 #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
15 #define RX_RING_SIZE 2
16
17 #define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/
18
19 /*
20 #define DEBUG_RX
21 #define DEBUG_TX
22 #define DEBUG_EEPROM
23 */
24
25 #define EPIC_DEBUG 0 /* debug level */
26
27 /* The EPIC100 Rx and Tx buffer descriptors. */
28 struct epic_rx_desc {
29 unsigned short status;
30 unsigned short rxlength;
31 unsigned long bufaddr;
32 unsigned short buflength;
33 unsigned short control;
34 unsigned long next;
35 };
36
37 /* description of the tx descriptors control bits commonly used */
38 #define TD_STDFLAGS TD_LASTDESC
39
40 struct epic_tx_desc {
41 unsigned short status;
42 unsigned short txlength;
43 unsigned long bufaddr;
44 unsigned short buflength;
45 unsigned short control;
46 unsigned long next;
47 };
48
49 #define delay(nanosec) do { int _i = 3; while (--_i > 0) \
50 { __SLOW_DOWN_IO; }} while (0)
51
52 static void epic100_open(void);
53 static void epic100_init_ring(void);
54 static void epic100_disable(struct nic *nic);
55 static int epic100_poll(struct nic *nic);
56 static void epic100_transmit(struct nic *nic, const char *destaddr,
57 unsigned int type, unsigned int len, const char *data);
58 static int read_eeprom(int location);
59 static int mii_read(int phy_id, int location);
60
61 static int ioaddr;
62
63 static int command;
64 static int intstat;
65 static int intmask;
66 static int genctl ;
67 static int eectl ;
68 static int test ;
69 static int mmctl ;
70 static int mmdata ;
71 static int lan0 ;
72 static int rxcon ;
73 static int txcon ;
74 static int prcdar ;
75 static int ptcdar ;
76 static int eththr ;
77
78 static unsigned int cur_rx, cur_tx; /* The next free ring entry */
79 #ifdef DEBUG_EEPROM
80 static unsigned short eeprom[64];
81 #endif
82 static signed char phys[4]; /* MII device addresses. */
83 static struct epic_rx_desc rx_ring[RX_RING_SIZE];
84 static struct epic_tx_desc tx_ring[TX_RING_SIZE];
85 #ifdef USE_LOWMEM_BUFFER
86 #define rx_packet ((char *)0x10000 - PKT_BUF_SZ * RX_RING_SIZE)
87 #define tx_packet ((char *)0x10000 - PKT_BUF_SZ * RX_RING_SIZE - PKT_BUF_SZ * TX_RING_SIZE)
88 #else
89 static char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
90 static char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
91 #endif
92
93 /***********************************************************************/
94 /* Externally visible functions */
95 /***********************************************************************/
96
97 static void
epic100_reset(struct nic * nic)98 epic100_reset(struct nic *nic)
99 {
100 /* Soft reset the chip. */
101 outl(GC_SOFT_RESET, genctl);
102 }
103
104 struct nic*
epic100_probe(struct nic * nic,unsigned short * probeaddrs)105 epic100_probe(struct nic *nic, unsigned short *probeaddrs)
106 {
107 unsigned short sum = 0;
108 unsigned short value;
109 int i;
110 unsigned short* ap;
111 unsigned int phy, phy_idx;
112
113 if (probeaddrs == 0 || probeaddrs[0] == 0)
114 return 0;
115
116 /* Ideally we would detect all network cards in slot order. That would
117 be best done a central PCI probe dispatch, which wouldn't work
118 well with the current structure. So instead we detect just the
119 Epic cards in slot order. */
120
121 ioaddr = probeaddrs[0] & ~3; /* Mask the bit that says "this is an io addr" */
122
123 /* compute all used static epic100 registers address */
124 command = ioaddr + COMMAND; /* Control Register */
125 intstat = ioaddr + INTSTAT; /* Interrupt Status */
126 intmask = ioaddr + INTMASK; /* Interrupt Mask */
127 genctl = ioaddr + GENCTL; /* General Control */
128 eectl = ioaddr + EECTL; /* EEPROM Control */
129 test = ioaddr + TEST; /* Test register (clocks) */
130 mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
131 mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
132 lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
133 rxcon = ioaddr + RXCON; /* Receive Control */
134 txcon = ioaddr + TXCON; /* Transmit Control */
135 prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
136 ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
137 eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
138
139 /* Reset the chip & bring it out of low-power mode. */
140 outl(GC_SOFT_RESET, genctl);
141
142 /* Disable ALL interrupts by setting the interrupt mask. */
143 outl(INTR_DISABLE, intmask);
144
145 /*
146 * set the internal clocks:
147 * Application Note 7.15 says:
148 * In order to set the CLOCK TEST bit in the TEST register,
149 * perform the following:
150 *
151 * Write 0x0008 to the test register at least sixteen
152 * consecutive times.
153 *
154 * The CLOCK TEST bit is Write-Only. Writing it several times
155 * consecutively insures a successful write to the bit...
156 */
157
158 for (i = 0; i < 16; i++) {
159 outl(0x00000008, test);
160 }
161
162 #ifdef DEBUG_EEPROM
163 for (i = 0; i < 64; i++) {
164 value = read_eeprom(i);
165 eeprom[i] = value;
166 sum += value;
167 }
168
169 #if (EPIC_DEBUG > 1)
170 printf("EEPROM contents\n");
171 for (i = 0; i < 64; i++) {
172 printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
173 }
174 #endif
175 #endif
176
177 /* This could also be read from the EEPROM. */
178 ap = (unsigned short*)nic->node_addr;
179 for (i = 0; i < 3; i++)
180 *ap++ = inw(lan0 + i*4);
181
182 printf(" I/O %#hX %! ", ioaddr, nic->node_addr);
183
184 /* Find the connected MII xcvrs. */
185 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
186 int mii_status = mii_read(phy, 0);
187
188 if (mii_status != 0xffff && mii_status != 0x0000) {
189 phys[phy_idx++] = phy;
190 #if (EPIC_DEBUG > 1)
191 printf("MII transceiver found at address %d.\n", phy);
192 #endif
193 }
194 }
195 if (phy_idx == 0) {
196 #if (EPIC_DEBUG > 1)
197 printf("***WARNING***: No MII transceiver found!\n");
198 #endif
199 /* Use the known PHY address of the EPII. */
200 phys[0] = 3;
201 }
202
203 epic100_open();
204
205 nic->reset = epic100_reset;
206 nic->poll = epic100_poll;
207 nic->transmit = epic100_transmit;
208 nic->disable = epic100_disable;
209
210 return nic;
211 }
212
213 static void
epic100_open(void)214 epic100_open(void)
215 {
216 int mii_reg5;
217 int full_duplex = 0;
218 unsigned long tmp;
219
220 epic100_init_ring();
221
222 /* Pull the chip out of low-power mode, and set for PCI read multiple. */
223 outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
224
225 outl(TX_FIFO_THRESH, eththr);
226
227 tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
228
229 mii_reg5 = mii_read(phys[0], 5);
230 if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
231 full_duplex = 1;
232 printf(" full-duplex mode");
233 tmp |= TC_LM_FULL_DPX;
234 } else
235 tmp |= TC_LM_NORMAL;
236
237 outl(tmp, txcon);
238
239 /* Give adress of RX and TX ring to the chip */
240 outl(virt_to_bus(&rx_ring), prcdar);
241 outl(virt_to_bus(&tx_ring), ptcdar);
242
243 /* Start the chip's Rx process: receive unicast and broadcast */
244 outl(0x04, rxcon);
245 outl(CR_START_RX | CR_QUEUE_RX, command);
246
247 putchar('\n');
248 }
249
250 /* Initialize the Rx and Tx rings. */
251 static void
epic100_init_ring(void)252 epic100_init_ring(void)
253 {
254 int i;
255 char* p;
256
257 cur_rx = cur_tx = 0;
258
259 p = &rx_packet[0];
260 for (i = 0; i < RX_RING_SIZE; i++) {
261 rx_ring[i].status = RRING_OWN; /* Owned by Epic chip */
262 rx_ring[i].buflength = PKT_BUF_SZ;
263 rx_ring[i].bufaddr = virt_to_bus(p + (PKT_BUF_SZ * i));
264 rx_ring[i].control = 0;
265 rx_ring[i].next = virt_to_bus(&(rx_ring[i + 1]) );
266 }
267 /* Mark the last entry as wrapping the ring. */
268 rx_ring[i-1].next = virt_to_bus(&rx_ring[0]);
269
270 /*
271 *The Tx buffer descriptor is filled in as needed,
272 * but we do need to clear the ownership bit.
273 */
274 p = &tx_packet[0];
275
276 for (i = 0; i < TX_RING_SIZE; i++) {
277 tx_ring[i].status = 0; /* Owned by CPU */
278 tx_ring[i].bufaddr = virt_to_bus(p + (PKT_BUF_SZ * i));
279 tx_ring[i].control = TD_STDFLAGS;
280 tx_ring[i].next = virt_to_bus(&(tx_ring[i + 1]) );
281 }
282 tx_ring[i-1].next = virt_to_bus(&tx_ring[0]);
283 }
284
285 /* function: epic100_transmit
286 * This transmits a packet.
287 *
288 * Arguments: char d[6]: destination ethernet address.
289 * unsigned short t: ethernet protocol type.
290 * unsigned short s: size of the data-part of the packet.
291 * char *p: the data for the packet.
292 * returns: void.
293 */
294 static void
epic100_transmit(struct nic * nic,const char * destaddr,unsigned int type,unsigned int len,const char * data)295 epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
296 unsigned int len, const char *data)
297 {
298 unsigned short nstype;
299 char* txp;
300 int entry;
301
302 /* Calculate the next Tx descriptor entry. */
303 entry = cur_tx % TX_RING_SIZE;
304
305 if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
306 printf("eth_transmit: Unable to transmit. status=%hX. Resetting...\n",
307 tx_ring[entry].status);
308
309 epic100_open();
310 return;
311 }
312
313 txp = (char*)tx_ring[entry].bufaddr;
314
315 memcpy(txp, destaddr, ETH_ALEN);
316 memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
317 nstype = htons(type);
318 memcpy(txp + 12, (char*)&nstype, 2);
319 memcpy(txp + ETH_HLEN, data, len);
320
321 len += ETH_HLEN;
322
323 /*
324 * Caution: the write order is important here,
325 * set the base address with the "ownership"
326 * bits last.
327 */
328 tx_ring[entry].txlength = (len >= 60 ? len : 60);
329 tx_ring[entry].buflength = len;
330 tx_ring[entry].status = TRING_OWN; /* Pass ownership to the chip. */
331
332 cur_tx++;
333
334 /* Trigger an immediate transmit demand. */
335 outl(CR_QUEUE_TX, command);
336
337 load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
338 while ((tx_ring[entry].status & TRING_OWN) && timer2_running())
339 /* Wait */;
340
341 if ((tx_ring[entry].status & TRING_OWN) != 0)
342 printf("Oops, transmitter timeout, status=%hX\n",
343 tx_ring[entry].status);
344 }
345
346 /* function: epic100_poll / eth_poll
347 * This receives a packet from the network.
348 *
349 * Arguments: none
350 *
351 * returns: 1 if a packet was received.
352 * 0 if no pacet was received.
353 * side effects:
354 * returns the packet in the array nic->packet.
355 * returns the length of the packet in nic->packetlen.
356 */
357
358 static int
epic100_poll(struct nic * nic)359 epic100_poll(struct nic *nic)
360 {
361 int entry;
362 int status;
363 int retcode;
364
365 entry = cur_rx % RX_RING_SIZE;
366
367 if ((status = rx_ring[entry].status & RRING_OWN) == RRING_OWN)
368 return (0);
369
370 /* We own the next entry, it's a new packet. Send it up. */
371
372 #if (EPIC_DEBUG > 4)
373 printf("epic_poll: entry %d status %hX\n", entry, status);
374 #endif
375
376 cur_rx++;
377 if (status & 0x2000) {
378 printf("epic_poll: Giant packet\n");
379 retcode = 0;
380 } else if (status & 0x0006) {
381 /* Rx Frame errors are counted in hardware. */
382 printf("epic_poll: Frame received with errors\n");
383 retcode = 0;
384 } else {
385 /* Omit the four octet CRC from the length. */
386 nic->packetlen = rx_ring[entry].rxlength - 4;
387 memcpy(nic->packet, (char*)rx_ring[entry].bufaddr, nic->packetlen);
388 retcode = 1;
389 }
390
391 /* Clear all error sources. */
392 outl(status & INTR_CLEARERRS, intstat);
393
394 /* Give the descriptor back to the chip */
395 rx_ring[entry].status = RRING_OWN;
396
397 /* Restart Receiver */
398 outl(CR_START_RX | CR_QUEUE_RX, command);
399
400 return retcode;
401 }
402
403
404 static void
epic100_disable(struct nic * nic)405 epic100_disable(struct nic *nic)
406 {
407 }
408
409
410 #ifdef DEBUG_EEPROM
411 /* Serial EEPROM section. */
412
413 /* EEPROM_Ctrl bits. */
414 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
415 #define EE_CS 0x02 /* EEPROM chip select. */
416 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
417 #define EE_WRITE_0 0x01
418 #define EE_WRITE_1 0x09
419 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
420 #define EE_ENB (0x0001 | EE_CS)
421
422 /* The EEPROM commands include the alway-set leading bit. */
423 #define EE_WRITE_CMD (5 << 6)
424 #define EE_READ_CMD (6 << 6)
425 #define EE_ERASE_CMD (7 << 6)
426
427 #define eeprom_delay(n) delay(n)
428
429 static int
read_eeprom(int location)430 read_eeprom(int location)
431 {
432 int i;
433 int retval = 0;
434 int read_cmd = location | EE_READ_CMD;
435
436 outl(EE_ENB & ~EE_CS, eectl);
437 outl(EE_ENB, eectl);
438
439 /* Shift the read command bits out. */
440 for (i = 10; i >= 0; i--) {
441 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
442 outl(EE_ENB | dataval, eectl);
443 eeprom_delay(100);
444 outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
445 eeprom_delay(150);
446 outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */
447 eeprom_delay(250);
448 }
449 outl(EE_ENB, eectl);
450
451 for (i = 16; i > 0; i--) {
452 outl(EE_ENB | EE_SHIFT_CLK, eectl);
453 eeprom_delay(100);
454 retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
455 outl(EE_ENB, eectl);
456 eeprom_delay(100);
457 }
458
459 /* Terminate the EEPROM access. */
460 outl(EE_ENB & ~EE_CS, eectl);
461 return retval;
462 }
463 #endif
464
465
466 #define MII_READOP 1
467 #define MII_WRITEOP 2
468
469 static int
mii_read(int phy_id,int location)470 mii_read(int phy_id, int location)
471 {
472 int i;
473
474 outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
475 /* Typical operation takes < 50 ticks. */
476
477 for (i = 4000; i > 0; i--)
478 if ((inl(mmctl) & MII_READOP) == 0)
479 break;
480 return inw(mmdata);
481 }
482