1 /* rhine.c:Fast Ethernet driver for Linux. */
2 /*
3 Adapted 09-jan-2000 by Paolo Marini (paolom@prisma-eng.it)
4
5 originally written by Donald Becker.
6
7 This software may be used and distributed according to the terms
8 of the GNU Public License (GPL), incorporated herein by reference.
9 Drivers derived from this code also fall under the GPL and must retain
10 this authorship and copyright notice.
11
12 Under no circumstances are the authors responsible for
13 the proper functioning of this software, nor do the authors assume any
14 responsibility for damages incurred with its use.
15
16 This driver is designed for the VIA VT86C100A Rhine-II PCI Fast Ethernet
17 controller.
18
19 */
20
21 static const char *version = "rhine.c v1.0.0 2000-01-07\n";
22
23 /* A few user-configurable values. */
24
25 /* Size of the in-memory receive ring. */
26 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K */
27 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
28
29 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
30 #define TX_BUF_SIZE 1536
31 #define RX_BUF_SIZE 1536
32
33 /* PCI Tuning Parameters
34 Threshold is bytes transferred to chip before transmission starts. */
35 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
36
37 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024. */
38 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
39 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
40 #define TX_DMA_BURST 4
41
42 /* Operational parameters that usually are not changed. */
43 /* Time in jiffies before concluding the transmitter is hung. */
44 #define TX_TIMEOUT ((2000*HZ)/1000)
45
46 #include "etherboot.h"
47 #include "nic.h"
48 #include "pci.h"
49 #include "cards.h"
50
51 /* define all ioaddr */
52
53 #define byPAR0 ioaddr
54 #define byRCR ioaddr + 6
55 #define byTCR ioaddr + 7
56 #define byCR0 ioaddr + 8
57 #define byCR1 ioaddr + 9
58 #define byISR0 ioaddr + 0x0c
59 #define byISR1 ioaddr + 0x0d
60 #define byIMR0 ioaddr + 0x0e
61 #define byIMR1 ioaddr + 0x0f
62 #define byMAR0 ioaddr + 0x10
63 #define byMAR1 ioaddr + 0x11
64 #define byMAR2 ioaddr + 0x12
65 #define byMAR3 ioaddr + 0x13
66 #define byMAR4 ioaddr + 0x14
67 #define byMAR5 ioaddr + 0x15
68 #define byMAR6 ioaddr + 0x16
69 #define byMAR7 ioaddr + 0x17
70 #define dwCurrentRxDescAddr ioaddr + 0x18
71 #define dwCurrentTxDescAddr ioaddr + 0x1c
72 #define dwCurrentRDSE0 ioaddr + 0x20
73 #define dwCurrentRDSE1 ioaddr + 0x24
74 #define dwCurrentRDSE2 ioaddr + 0x28
75 #define dwCurrentRDSE3 ioaddr + 0x2c
76 #define dwNextRDSE0 ioaddr + 0x30
77 #define dwNextRDSE1 ioaddr + 0x34
78 #define dwNextRDSE2 ioaddr + 0x38
79 #define dwNextRDSE3 ioaddr + 0x3c
80 #define dwCurrentTDSE0 ioaddr + 0x40
81 #define dwCurrentTDSE1 ioaddr + 0x44
82 #define dwCurrentTDSE2 ioaddr + 0x48
83 #define dwCurrentTDSE3 ioaddr + 0x4c
84 #define dwNextTDSE0 ioaddr + 0x50
85 #define dwNextTDSE1 ioaddr + 0x54
86 #define dwNextTDSE2 ioaddr + 0x58
87 #define dwNextTDSE3 ioaddr + 0x5c
88 #define dwCurrRxDMAPtr ioaddr + 0x60
89 #define dwCurrTxDMAPtr ioaddr + 0x64
90 #define byMPHY ioaddr + 0x6c
91 #define byMIISR ioaddr + 0x6d
92 #define byBCR0 ioaddr + 0x6e
93 #define byBCR1 ioaddr + 0x6f
94 #define byMIICR ioaddr + 0x70
95 #define byMIIAD ioaddr + 0x71
96 #define wMIIDATA ioaddr + 0x72
97 #define byEECSR ioaddr + 0x74
98 #define byTEST ioaddr + 0x75
99 #define byGPIO ioaddr + 0x76
100 #define byCFGA ioaddr + 0x78
101 #define byCFGB ioaddr + 0x79
102 #define byCFGC ioaddr + 0x7a
103 #define byCFGD ioaddr + 0x7b
104 #define wTallyCntMPA ioaddr + 0x7c
105 #define wTallyCntCRC ioaddr + 0x7d
106 /*--------------------- Exioaddr Definitions -------------------------*/
107
108 /*
109 * Bits in the RCR register
110 */
111
112 #define RCR_RRFT2 0x80
113 #define RCR_RRFT1 0x40
114 #define RCR_RRFT0 0x20
115 #define RCR_PROM 0x10
116 #define RCR_AB 0x08
117 #define RCR_AM 0x04
118 #define RCR_AR 0x02
119 #define RCR_SEP 0x01
120
121 /*
122 * Bits in the TCR register
123 */
124
125 #define TCR_RTSF 0x80
126 #define TCR_RTFT1 0x40
127 #define TCR_RTFT0 0x20
128 #define TCR_OFSET 0x08
129 #define TCR_LB1 0x04 /* loopback[1] */
130 #define TCR_LB0 0x02 /* loopback[0] */
131
132 /*
133 * Bits in the CR0 register
134 */
135
136 #define CR0_RDMD 0x40 /* rx descriptor polling demand */
137 #define CR0_TDMD 0x20 /* tx descriptor polling demand */
138 #define CR0_TXON 0x10
139 #define CR0_RXON 0x08
140 #define CR0_STOP 0x04 /* stop NIC, default = 1 */
141 #define CR0_STRT 0x02 /* start NIC */
142 #define CR0_INIT 0x01 /* start init process */
143
144
145 /*
146 * Bits in the CR1 register
147 */
148
149 #define CR1_SFRST 0x80 /* software reset */
150 #define CR1_RDMD1 0x40 /* RDMD1 */
151 #define CR1_TDMD1 0x20 /* TDMD1 */
152 #define CR1_KEYPAG 0x10 /* turn on par/key */
153 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
154 #define CR1_FDX 0x04 /* full duplex mode */
155 #define CR1_ETEN 0x02 /* early tx mode */
156 #define CR1_EREN 0x01 /* early rx mode */
157
158 /*
159 * Bits in the CR register
160 */
161
162 #define CR_RDMD 0x0040 /* rx descriptor polling demand */
163 #define CR_TDMD 0x0020 /* tx descriptor polling demand */
164 #define CR_TXON 0x0010
165 #define CR_RXON 0x0008
166 #define CR_STOP 0x0004 /* stop NIC, default = 1 */
167 #define CR_STRT 0x0002 /* start NIC */
168 #define CR_INIT 0x0001 /* start init process */
169 #define CR_SFRST 0x8000 /* software reset */
170 #define CR_RDMD1 0x4000 /* RDMD1 */
171 #define CR_TDMD1 0x2000 /* TDMD1 */
172 #define CR_KEYPAG 0x1000 /* turn on par/key */
173 #define CR_DPOLL 0x0800 /* disable rx/tx auto polling */
174 #define CR_FDX 0x0400 /* full duplex mode */
175 #define CR_ETEN 0x0200 /* early tx mode */
176 #define CR_EREN 0x0100 /* early rx mode */
177
178 /*
179 * Bits in the IMR0 register
180 */
181
182 #define IMR0_CNTM 0x80
183 #define IMR0_BEM 0x40
184 #define IMR0_RUM 0x20
185 #define IMR0_TUM 0x10
186 #define IMR0_TXEM 0x08
187 #define IMR0_RXEM 0x04
188 #define IMR0_PTXM 0x02
189 #define IMR0_PRXM 0x01
190
191 /* define imrshadow */
192
193 #define IMRShadow 0x5AFF
194
195 /*
196 * Bits in the IMR1 register
197 */
198
199 #define IMR1_INITM 0x80
200 #define IMR1_SRCM 0x40
201 #define IMR1_NBFM 0x10
202 #define IMR1_PRAIM 0x08
203 #define IMR1_RES0M 0x04
204 #define IMR1_ETM 0x02
205 #define IMR1_ERM 0x01
206
207 /*
208 * Bits in the ISR register
209 */
210
211 #define ISR_INITI 0x8000
212 #define ISR_SRCI 0x4000
213 #define ISR_ABTI 0x2000
214 #define ISR_NORBF 0x1000
215 #define ISR_PKTRA 0x0800
216 #define ISR_RES0 0x0400
217 #define ISR_ETI 0x0200
218 #define ISR_ERI 0x0100
219 #define ISR_CNT 0x0080
220 #define ISR_BE 0x0040
221 #define ISR_RU 0x0020
222 #define ISR_TU 0x0010
223 #define ISR_TXE 0x0008
224 #define ISR_RXE 0x0004
225 #define ISR_PTX 0x0002
226 #define ISR_PRX 0x0001
227
228 /*
229 * Bits in the ISR0 register
230 */
231
232 #define ISR0_CNT 0x80
233 #define ISR0_BE 0x40
234 #define ISR0_RU 0x20
235 #define ISR0_TU 0x10
236 #define ISR0_TXE 0x08
237 #define ISR0_RXE 0x04
238 #define ISR0_PTX 0x02
239 #define ISR0_PRX 0x01
240
241 /*
242 * Bits in the ISR1 register
243 */
244
245 #define ISR1_INITI 0x80
246 #define ISR1_SRCI 0x40
247 #define ISR1_NORBF 0x10
248 #define ISR1_PKTRA 0x08
249 #define ISR1_ETI 0x02
250 #define ISR1_ERI 0x01
251
252 /* ISR ABNORMAL CONDITION */
253
254 #define ISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA
255
256 /*
257 * Bits in the MIISR register
258 */
259
260 #define MIISR_MIIERR 0x08
261 #define MIISR_MRERR 0x04
262 #define MIISR_LNKFL 0x02
263 #define MIISR_SPEED 0x01
264
265 /*
266 * Bits in the MIICR register
267 */
268
269 #define MIICR_MAUTO 0x80
270 #define MIICR_RCMD 0x40
271 #define MIICR_WCMD 0x20
272 #define MIICR_MDPM 0x10
273 #define MIICR_MOUT 0x08
274 #define MIICR_MDO 0x04
275 #define MIICR_MDI 0x02
276 #define MIICR_MDC 0x01
277
278 /*
279 * Bits in the EECSR register
280 */
281
282 #define EECSR_EEPR 0x80 /* eeprom programed status, 73h means programed */
283 #define EECSR_EMBP 0x40 /* eeprom embeded programming */
284 #define EECSR_AUTOLD 0x20 /* eeprom content reload */
285 #define EECSR_DPM 0x10 /* eeprom direct programming */
286 #define EECSR_CS 0x08 /* eeprom CS pin */
287 #define EECSR_SK 0x04 /* eeprom SK pin */
288 #define EECSR_DI 0x02 /* eeprom DI pin */
289 #define EECSR_DO 0x01 /* eeprom DO pin */
290
291 /*
292 * Bits in the BCR0 register
293 */
294
295 #define BCR0_CRFT2 0x20
296 #define BCR0_CRFT1 0x10
297 #define BCR0_CRFT0 0x08
298 #define BCR0_DMAL2 0x04
299 #define BCR0_DMAL1 0x02
300 #define BCR0_DMAL0 0x01
301
302 /*
303 * Bits in the BCR1 register
304 */
305
306 #define BCR1_CTSF 0x20
307 #define BCR1_CTFT1 0x10
308 #define BCR1_CTFT0 0x08
309 #define BCR1_POT2 0x04
310 #define BCR1_POT1 0x02
311 #define BCR1_POT0 0x01
312
313 /*
314 * Bits in the CFGA register
315 */
316
317 #define CFGA_EELOAD 0x80 /* enable eeprom embeded and direct programming */
318 #define CFGA_JUMPER 0x40
319 #define CFGA_MTGPIO 0x08
320 #define CFGA_T10EN 0x02
321 #define CFGA_AUTO 0x01
322
323 /*
324 * Bits in the CFGB register
325 */
326
327 #define CFGB_PD 0x80
328 #define CFGB_POLEN 0x02
329 #define CFGB_LNKEN 0x01
330
331 /*
332 * Bits in the CFGC register
333 */
334
335 #define CFGC_M10TIO 0x80
336 #define CFGC_M10POL 0x40
337 #define CFGC_PHY1 0x20
338 #define CFGC_PHY0 0x10
339 #define CFGC_BTSEL 0x08
340 #define CFGC_BPS2 0x04 /* bootrom select[2] */
341 #define CFGC_BPS1 0x02 /* bootrom select[1] */
342 #define CFGC_BPS0 0x01 /* bootrom select[0] */
343
344 /*
345 * Bits in the CFGD register
346 */
347
348 #define CFGD_GPIOEN 0x80
349 #define CFGD_DIAG 0x40
350 #define CFGD_MAGIC 0x10
351 #define CFGD_CFDX 0x04
352 #define CFGD_CEREN 0x02
353 #define CFGD_CETEN 0x01
354
355 /* Bits in RSR */
356 #define RSR_RERR 0x00000001
357 #define RSR_CRC 0x00000002
358 #define RSR_FAE 0x00000004
359 #define RSR_FOV 0x00000008
360 #define RSR_LONG 0x00000010
361 #define RSR_RUNT 0x00000020
362 #define RSR_SERR 0x00000040
363 #define RSR_BUFF 0x00000080
364 #define RSR_EDP 0x00000100
365 #define RSR_STP 0x00000200
366 #define RSR_CHN 0x00000400
367 #define RSR_PHY 0x00000800
368 #define RSR_BAR 0x00001000
369 #define RSR_MAR 0x00002000
370 #define RSR_RXOK 0x00008000
371 #define RSR_ABNORMAL RSR_RERR+RSR_LONG+RSR_RUNT
372
373 /* Bits in TSR */
374 #define TSR_NCR0 0x00000001
375 #define TSR_NCR1 0x00000002
376 #define TSR_NCR2 0x00000004
377 #define TSR_NCR3 0x00000008
378 #define TSR_COLS 0x00000010
379 #define TSR_CDH 0x00000080
380 #define TSR_ABT 0x00000100
381 #define TSR_OWC 0x00000200
382 #define TSR_CRS 0x00000400
383 #define TSR_UDF 0x00000800
384 #define TSR_TBUFF 0x00001000
385 #define TSR_SERR 0x00002000
386 #define TSR_JAB 0x00004000
387 #define TSR_TERR 0x00008000
388 #define TSR_ABNORMAL TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS
389 #define TSR_OWN_BIT 0x80000000
390
391 #define CB_DELAY_LOOP_WAIT 10 /* 10ms */
392 /* enabled mask value of irq */
393
394 #define W_IMR_MASK_VALUE 0x1BFF /* initial value of IMR */
395
396 /* Ethernet address filter type */
397 #define PKT_TYPE_DIRECTED 0x0001 /* obsolete, directed address is always accepted */
398 #define PKT_TYPE_MULTICAST 0x0002
399 #define PKT_TYPE_ALL_MULTICAST 0x0004
400 #define PKT_TYPE_BROADCAST 0x0008
401 #define PKT_TYPE_PROMISCUOUS 0x0020
402 #define PKT_TYPE_LONG 0x2000
403 #define PKT_TYPE_RUNT 0x4000
404 #define PKT_TYPE_ERROR 0x8000 /* accept error packets, e.g. CRC error */
405
406 /* Loopback mode */
407
408 #define NIC_LB_NONE 0x00
409 #define NIC_LB_INTERNAL 0x01
410 #define NIC_LB_PHY 0x02 /* MII or Internal-10BaseT loopback */
411
412 #define TX_RING_SIZE 2
413 #define RX_RING_SIZE 2
414 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
415
416 /* Transmit and receive descriptors definition */
417
418 struct rhine_tx_desc
419 {
420 union VTC_tx_status_tag
421 {
422 struct
423 {
424 unsigned long ncro:1;
425 unsigned long ncr1:1;
426 unsigned long ncr2:1;
427 unsigned long ncr3:1;
428 unsigned long cols:1;
429 unsigned long reserve_1:2;
430 unsigned long cdh:1;
431 unsigned long abt:1;
432 unsigned long owc:1;
433 unsigned long crs:1;
434 unsigned long udf:1;
435 unsigned long tbuff:1;
436 unsigned long serr:1;
437 unsigned long jab:1;
438 unsigned long terr:1;
439 unsigned long reserve_2:15;
440 unsigned long own_bit:1;
441 }
442 bits;
443 unsigned long lw;
444 }
445 tx_status;
446
447 union VTC_tx_ctrl_tag
448 {
449 struct
450 {
451 unsigned long tx_buf_size:11;
452 unsigned long extend_tx_buf_size:4;
453 unsigned long chn:1;
454 unsigned long crc:1;
455 unsigned long reserve_1:4;
456 unsigned long stp:1;
457 unsigned long edp:1;
458 unsigned long ic:1;
459 unsigned long reserve_2:8;
460 }
461 bits;
462 unsigned long lw;
463 }
464 tx_ctrl;
465
466 unsigned long buf_addr_1:32;
467 unsigned long buf_addr_2:32;
468
469 };
470
471 struct rhine_rx_desc
472 {
473 union VTC_rx_status_tag
474 {
475 struct
476 {
477 unsigned long rerr:1;
478 unsigned long crc_error:1;
479 unsigned long fae:1;
480 unsigned long fov:1;
481 unsigned long toolong:1;
482 unsigned long runt:1;
483 unsigned long serr:1;
484 unsigned long buff:1;
485 unsigned long edp:1;
486 unsigned long stp:1;
487 unsigned long chn:1;
488 unsigned long phy:1;
489 unsigned long bar:1;
490 unsigned long mar:1;
491 unsigned long reserve_1:1;
492 unsigned long rxok:1;
493 unsigned long frame_length:11;
494 unsigned long reverve_2:4;
495 unsigned long own_bit:1;
496 }
497 bits;
498 unsigned long lw;
499 }
500 rx_status;
501
502 union VTC_rx_ctrl_tag
503 {
504 struct
505 {
506 unsigned long rx_buf_size:11;
507 unsigned long extend_rx_buf_size:4;
508 unsigned long reserved_1:17;
509 }
510 bits;
511 unsigned long lw;
512 }
513 rx_ctrl;
514
515 unsigned long buf_addr_1:32;
516 unsigned long buf_addr_2:32;
517
518 };
519
520
521 /* The I/O extent. */
522 #define rhine_TOTAL_SIZE 0x80
523
524 #ifdef HAVE_DEVLIST
525 struct netdev_entry rhine_drv =
526 { "rhine", rhine_probe, rhine_TOTAL_SIZE, NULL };
527 #endif
528
529 static int rhine_debug = 1;
530
531 /*
532 Theory of Operation
533
534 I. Board Compatibility
535
536 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
537 controller.
538
539 II. Board-specific settings
540
541 Boards with this chip are functional only in a bus-master PCI slot.
542
543 Many operational settings are loaded from the EEPROM to the Config word at
544 offset 0x78. This driver assumes that they are correct.
545 If this driver is compiled to use PCI memory space operations the EEPROM
546 must be configured to enable memory ops.
547
548 III. Driver operation
549
550 IIIa. Ring buffers
551
552 This driver uses two statically allocated fixed-size descriptor lists
553 formed into rings by a branch from the final descriptor to the beginning of
554 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
555
556 IIIb/c. Transmit/Receive Structure
557
558 This driver attempts to use a zero-copy receive and transmit scheme.
559
560 Alas, all data buffers are required to start on a 32 bit boundary, so
561 the driver must often copy transmit packets into bounce buffers.
562
563 The driver allocates full frame size skbuffs for the Rx ring buffers at
564 open() time and passes the skb->data field to the chip as receive data
565 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
566 a fresh skbuff is allocated and the frame is copied to the new skbuff.
567 When the incoming frame is larger, the skbuff is passed directly up the
568 protocol stack. Buffers consumed this way are replaced by newly allocated
569 skbuffs in the last phase of netdev_rx().
570
571 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
572 using a full-sized skbuff for small frames vs. the copying costs of larger
573 frames. New boards are typically used in generously configured machines
574 and the underfilled buffers have negligible impact compared to the benefit of
575 a single allocation size, so the default value of zero results in never
576 copying packets. When copying is done, the cost is usually mitigated by using
577 a combined copy/checksum routine. Copying also preloads the cache, which is
578 most useful with small frames.
579
580 Since the VIA chips are only able to transfer data to buffers on 32 bit
581 boundaries, the the IP header at offset 14 in an ethernet frame isn't
582 longword aligned for further processing. Copying these unaligned buffers
583 has the beneficial effect of 16-byte aligning the IP header.
584
585 IIId. Synchronization
586
587 The driver runs as two independent, single-threaded flows of control. One
588 is the send-packet routine, which enforces single-threaded use by the
589 dev->tbusy flag. The other thread is the interrupt handler, which is single
590 threaded by the hardware and interrupt handling software.
591
592 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
593 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
594 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
595 the 'lp->tx_full' flag.
596
597 The interrupt handler has exclusive control over the Rx ring and records stats
598 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
599 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
600 clears both the tx_full and tbusy flags.
601
602 IV. Notes
603
604 IVb. References
605
606 Preliminary VT86C100A manual from http://www.via.com.tw/
607 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
608 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
609
610 IVc. Errata
611
612 The VT86C100A manual is not reliable information.
613 The chip does not handle unaligned transmit or receive buffers, resulting
614 in significant performance degradation for bounce buffer copies on transmit
615 and unaligned IP headers on receive.
616 The chip does not pad to minimum transmit length.
617
618 */
619
620 #define PCI_VENDOR_ID_FET 0x1106
621 #define PCI_DEVICE_ID_FET_3043 0x3043
622
623 /* The rest of these values should never change. */
624 #define NUM_TX_DESC 2 /* Number of Tx descriptor registers. */
625
626 static struct rhine_private
627 {
628 char devname[8]; /* Used only for kernel debugging. */
629 const char *product_name;
630 struct rhine_rx_desc *rx_ring;
631 struct rhine_tx_desc *tx_ring;
632 char *rx_buffs[RX_RING_SIZE];
633 char *tx_buffs[TX_RING_SIZE];
634
635 /* temporary Rx buffers. */
636
637 int chip_id;
638 int chip_revision;
639 unsigned short ioaddr;
640 unsigned int cur_rx, cur_tx; /* The next free and used entries */
641 unsigned int dirty_rx, dirty_tx;
642 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
643 struct sk_buff *tx_skbuff[TX_RING_SIZE];
644 unsigned char mc_filter[8]; /* Current multicast filter. */
645 char phys[4]; /* MII device addresses. */
646 unsigned int tx_full:1; /* The Tx queue is full. */
647 unsigned int full_duplex:1; /* Full-duplex operation requested. */
648 unsigned int default_port:4; /* Last dev->if_port value. */
649 unsigned int media2:4; /* Secondary monitored media port. */
650 unsigned int medialock:1; /* Don't sense media type. */
651 unsigned int mediasense:1; /* Media sensing in progress. */
652 }
653 rhine;
654
655 static struct nic *rhine_probe1 (struct nic *dev, int ioaddr,
656 int chip_id, int options);
657 static int QueryAuto (int);
658 static int ReadMII (int byMIIIndex, int);
659 static void WriteMII (char, char, char, int);
660 static void MIIDelay (void);
661 static void rhine_init_ring (struct nic *dev);
662 static void rhine_disable (struct nic *nic);
663 static void rhine_reset (struct nic *nic);
664 static int rhine_poll (struct nic *nic);
665 static void rhine_transmit (struct nic *nic, const char *d, unsigned int t,
666 unsigned int s, const char *p);
667
668 /* Linux support functions */
669 #define virt_to_bus(x) ((unsigned long)x)
670 #define bus_to_virt(x) ((void *)x)
671
672 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
673 static void
rhine_init_ring(struct nic * nic)674 rhine_init_ring (struct nic *nic)
675 {
676 struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
677 int i;
678
679 tp->tx_full = 0;
680 tp->cur_rx = tp->cur_tx = 0;
681 tp->dirty_rx = tp->dirty_tx = 0;
682
683 for (i = 0; i < RX_RING_SIZE; i++)
684 {
685
686 tp->rx_ring[i].rx_status.bits.own_bit = 1;
687 tp->rx_ring[i].rx_ctrl.bits.rx_buf_size = 1536;
688
689 tp->rx_ring[i].buf_addr_1 = virt_to_bus (tp->rx_buffs[i]);
690 tp->rx_ring[i].buf_addr_2 = virt_to_bus (&tp->rx_ring[i + 1]);
691 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->rx_ring[i].buf_addr_1,tp->rx_ring[i].buf_addr_2); */
692 }
693 /* Mark the last entry as wrapping the ring. */
694 /* tp->rx_ring[i-1].rx_ctrl.bits.rx_buf_size =1518; */
695 tp->rx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->rx_ring[0]);
696 /*printf("[%d]buf1=%hX,buf2=%hX",i-1,tp->rx_ring[i-1].buf_addr_1,tp->rx_ring[i-1].buf_addr_2); */
697
698 /* The Tx buffer descriptor is filled in as needed, but we
699 do need to clear the ownership bit. */
700
701 for (i = 0; i < TX_RING_SIZE; i++)
702 {
703
704 tp->tx_ring[i].tx_status.lw = 0;
705 tp->tx_ring[i].tx_ctrl.lw = 0x00e08000;
706 tp->tx_ring[i].buf_addr_1 = virt_to_bus (tp->tx_buffs[i]);
707 tp->tx_ring[i].buf_addr_2 = virt_to_bus (&tp->tx_ring[i + 1]);
708 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i].buf_addr_1,tp->tx_ring[i].buf_addr_2); */
709 }
710
711 tp->tx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->tx_ring[0]);
712 /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i-1].buf_addr_1,tp->tx_ring[i-1].buf_addr_2); */
713 }
714
715 int
QueryAuto(int ioaddr)716 QueryAuto (int ioaddr)
717 {
718 int byMIIIndex;
719 int MIIReturn;
720
721 int advertising,mii_reg5;
722 int negociated;
723
724 byMIIIndex = 0x04;
725 MIIReturn = ReadMII (byMIIIndex, ioaddr);
726 advertising=MIIReturn;
727
728 byMIIIndex = 0x05;
729 MIIReturn = ReadMII (byMIIIndex, ioaddr);
730 mii_reg5=MIIReturn;
731
732 negociated=mii_reg5 & advertising;
733
734 if ( (negociated & 0x100) || (negociated & 0x1C0) == 0x40 )
735 return 1;
736 else
737 return 0;
738
739 }
740
741 int
ReadMII(int byMIIIndex,int ioaddr)742 ReadMII (int byMIIIndex, int ioaddr)
743 {
744 int ReturnMII;
745 char byMIIAdrbak;
746 char byMIICRbak;
747 char byMIItemp;
748
749 byMIIAdrbak = inb (byMIIAD);
750 byMIICRbak = inb (byMIICR);
751 outb (byMIICRbak & 0x7f, byMIICR);
752 MIIDelay ();
753
754 outb (byMIIIndex, byMIIAD);
755 MIIDelay ();
756
757 outb (inb (byMIICR) | 0x40, byMIICR);
758
759 byMIItemp = inb (byMIICR);
760 byMIItemp = byMIItemp & 0x40;
761
762 while (byMIItemp != 0)
763 {
764 byMIItemp = inb (byMIICR);
765 byMIItemp = byMIItemp & 0x40;
766 }
767 MIIDelay ();
768
769 ReturnMII = inw (wMIIDATA);
770
771 outb (byMIIAdrbak, byMIIAD);
772 outb (byMIICRbak, byMIICR);
773 MIIDelay ();
774
775 return (ReturnMII);
776
777 }
778
779 void
WriteMII(char byMIISetByte,char byMIISetBit,char byMIIOP,int ioaddr)780 WriteMII (char byMIISetByte, char byMIISetBit, char byMIIOP, int ioaddr)
781 {
782 int ReadMIItmp;
783 int MIIMask;
784 char byMIIAdrbak;
785 char byMIICRbak;
786 char byMIItemp;
787
788
789 byMIIAdrbak = inb (byMIIAD);
790
791 byMIICRbak = inb (byMIICR);
792 outb (byMIICRbak & 0x7f, byMIICR);
793 MIIDelay ();
794 outb (byMIISetByte, byMIIAD);
795 MIIDelay ();
796
797 outb (inb (byMIICR) | 0x40, byMIICR);
798
799 byMIItemp = inb (byMIICR);
800 byMIItemp = byMIItemp & 0x40;
801
802 while (byMIItemp != 0)
803 {
804 byMIItemp = inb (byMIICR);
805 byMIItemp = byMIItemp & 0x40;
806 }
807 MIIDelay ();
808
809 ReadMIItmp = inw (wMIIDATA);
810 MIIMask = 0x0001;
811 MIIMask = MIIMask << byMIISetBit;
812
813
814 if (byMIIOP == 0)
815 {
816 MIIMask = ~MIIMask;
817 ReadMIItmp = ReadMIItmp & MIIMask;
818 }
819 else
820 {
821 ReadMIItmp = ReadMIItmp | MIIMask;
822
823 }
824 outw (ReadMIItmp, wMIIDATA);
825 MIIDelay ();
826
827 outb (inb (byMIICR) | 0x20, byMIICR);
828 byMIItemp = inb (byMIICR);
829 byMIItemp = byMIItemp & 0x20;
830
831 while (byMIItemp != 0)
832 {
833 byMIItemp = inb (byMIICR);
834 byMIItemp = byMIItemp & 0x20;
835 }
836 MIIDelay ();
837
838 outb (byMIIAdrbak & 0x7f, byMIIAD);
839 outb (byMIICRbak, byMIICR);
840 MIIDelay ();
841
842 }
843
844 void
MIIDelay(void)845 MIIDelay (void)
846 {
847 int i;
848 for (i = 0; i < 0x7fff; i++)
849 {
850 inb (0x61);
851 inb (0x61);
852 inb (0x61);
853 inb (0x61);
854 }
855 }
856
857 struct nic *
rhine_probe(struct nic * nic,unsigned short * probeaddrs,struct pci_device * pci)858 rhine_probe (struct nic *nic, unsigned short *probeaddrs,
859 struct pci_device *pci)
860 {
861 if (!pci->ioaddr)
862 return NULL;
863 nic = rhine_probe1 (nic, pci->ioaddr, 0, -1);
864
865 if (nic)
866 adjust_pci_device(pci);
867 nic->poll = rhine_poll;
868 nic->transmit = rhine_transmit;
869 nic->reset = rhine_reset;
870 nic->disable = rhine_disable;
871 rhine_reset (nic);
872
873 return nic;
874 }
875
876 static struct nic *
rhine_probe1(struct nic * nic,int ioaddr,int chip_id,int options)877 rhine_probe1 (struct nic *nic, int ioaddr, int chip_id, int options)
878 {
879 struct rhine_private *tp;
880 static int did_version = 0; /* Already printed version info. */
881 int i;
882 unsigned int timeout;
883 int FDXFlag;
884 int byMIIvalue, LineSpeed, MIICRbak;
885
886 if (rhine_debug > 0 && did_version++ == 0)
887 printf (version);
888 /* Perhaps this should be read from the EEPROM? */
889 for (i = 0; i < ETH_ALEN; i++)
890 nic->node_addr[i] = inb (byPAR0 + i);
891 printf ("IO address %hX Ethernet Address: %!\n", ioaddr, nic->node_addr);
892
893 /* restart MII auto-negotiation */
894 WriteMII (0, 9, 1, ioaddr);
895 printf ("Analyzing Media type,this will take several seconds........");
896 for (i = 0; i < 5; i++)
897 {
898 /* need to wait 1 millisecond - we will round it up to 50-100ms */
899 timeout = currticks() + 2;
900 for (timeout = currticks() + 2; currticks() < timeout;)
901 /* nothing */;
902 if (ReadMII (1, ioaddr) & 0x0020)
903 break;
904 }
905 printf ("OK\n");
906
907 #if 0
908 /* JJM : for Debug */
909 printf("MII : Address %hhX ",inb(ioaddr+0x6c));
910 {
911 unsigned char st1,st2,adv1,adv2,l1,l2;
912
913 st1=ReadMII(1,ioaddr)>>8;
914 st2=ReadMII(1,ioaddr)&0xFF;
915 adv1=ReadMII(4,ioaddr)>>8;
916 adv2=ReadMII(4,ioaddr)&0xFF;
917 l1=ReadMII(5,ioaddr)>>8;
918 l2=ReadMII(5,ioaddr)&0xFF;
919 printf(" status 0x%hhX%hhX, advertising 0x%hhX%hhX, link 0x%hhX%hhX\n", st1,st2,adv1,adv2,l1,l2);
920 }
921 #endif
922
923 /* query MII to know LineSpeed,duplex mode */
924 byMIIvalue = inb (ioaddr + 0x6d);
925 LineSpeed = byMIIvalue & MIISR_SPEED;
926 if (LineSpeed != 0) //JJM
927 {
928 printf ("Linespeed=10Mbs");
929 }
930 else
931 {
932 printf ("Linespeed=100Mbs");
933 }
934
935 FDXFlag = QueryAuto (ioaddr);
936 if (FDXFlag == 1)
937 {
938 printf (" Fullduplex\n");
939 outw (CR_FDX, byCR0);
940 }
941 else
942 {
943 printf (" Halfduplex\n");
944 }
945
946
947 /* set MII 10 FULL ON */
948 WriteMII (17, 1, 1, ioaddr);
949
950 /* turn on MII link change */
951 MIICRbak = inb (byMIICR);
952 outb (MIICRbak & 0x7F, byMIICR);
953 MIIDelay ();
954 outb (0x41, byMIIAD);
955 MIIDelay ();
956
957 /* while((inb(byMIIAD)&0x20)==0) ; */
958 outb (MIICRbak | 0x80, byMIICR);
959
960 nic->priv_data = &rhine;
961 tp = &rhine;
962 tp->chip_id = chip_id;
963 tp->ioaddr = ioaddr;
964 tp->phys[0] = -1;
965
966 /* The lower four bits are the media type. */
967 if (options > 0)
968 {
969 tp->full_duplex = (options & 16) ? 1 : 0;
970 tp->default_port = options & 15;
971 if (tp->default_port)
972 tp->medialock = 1;
973 }
974 return nic;
975 }
976
977 static void
rhine_disable(struct nic * nic)978 rhine_disable (struct nic *nic)
979 {
980 struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
981 int ioaddr = tp->ioaddr;
982
983 printf ("rhine disable\n");
984 /* Switch to loopback mode to avoid hardware races. */
985 writeb(0x60 | 0x01, byTCR);
986 /* Stop the chip's Tx and Rx processes. */
987 writew(CR_STOP, byCR0);
988 }
989
990 /**************************************************************************
991 ETH_RESET - Reset adapter
992 ***************************************************************************/
993 static void
rhine_reset(struct nic * nic)994 rhine_reset (struct nic *nic)
995 {
996 struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
997 int ioaddr = tp->ioaddr;
998 int i, j;
999 int FDXFlag, CRbak;
1000 int rx_ring_tmp, rx_ring_tmp1;
1001 int tx_ring_tmp, tx_ring_tmp1;
1002 int rx_bufs_tmp, rx_bufs_tmp1;
1003 int tx_bufs_tmp, tx_bufs_tmp1;
1004
1005 #ifdef USE_LOWMEM_BUFFER
1006 #define buf1 (0x10000 - (RX_RING_SIZE * PKT_BUF_SZ + 32))
1007 #define buf2 (buf1 - (RX_RING_SIZE * PKT_BUF_SZ + 32))
1008 #define desc1 (buf2 - (TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32))
1009 #define desc2 (desc1 - (TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32))
1010 #else
1011 static char buf1[RX_RING_SIZE * PKT_BUF_SZ + 32];
1012 static char buf2[RX_RING_SIZE * PKT_BUF_SZ + 32];
1013 static char desc1[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32];
1014 static char desc2[TX_RING_SIZE * sizeof (struct rhine_tx_desc) + 32];
1015 #endif
1016
1017 /* printf ("rhine_reset\n"); */
1018 /* Soft reset the chip. */
1019 /*outb(CmdReset, ioaddr + ChipCmd); */
1020
1021 tx_bufs_tmp = (int) buf1;
1022 tx_ring_tmp = (int) desc1;
1023 rx_bufs_tmp = (int) buf2;
1024 rx_ring_tmp = (int) desc2;
1025
1026 /* tune RD TD 32 byte alignment */
1027 rx_ring_tmp1 = (int) virt_to_bus ((char *) rx_ring_tmp);
1028 j = (rx_ring_tmp1 + 32) & (~0x1f);
1029 /* printf ("txring[%d]", j); */
1030 tp->rx_ring = (struct rhine_rx_desc *) bus_to_virt (j);
1031
1032 tx_ring_tmp1 = (int) virt_to_bus ((char *) tx_ring_tmp);
1033 j = (tx_ring_tmp1 + 32) & (~0x1f);
1034 tp->tx_ring = (struct rhine_tx_desc *) bus_to_virt (j);
1035 /* printf ("rxring[%X]", j); */
1036
1037
1038 tx_bufs_tmp1 = (int) virt_to_bus ((char *) tx_bufs_tmp);
1039 j = (int) (tx_bufs_tmp1 + 32) & (~0x1f);
1040 tx_bufs_tmp = (int) bus_to_virt (j);
1041 /* printf ("txb[%X]", j); */
1042
1043 rx_bufs_tmp1 = (int) virt_to_bus ((char *) rx_bufs_tmp);
1044 j = (int) (rx_bufs_tmp1 + 32) & (~0x1f);
1045 rx_bufs_tmp = (int) bus_to_virt (j);
1046 /* printf ("rxb[%X][%X]", rx_bufs_tmp1, j); */
1047
1048 for (i = 0; i < RX_RING_SIZE; i++)
1049 {
1050 tp->rx_buffs[i] = (char *) rx_bufs_tmp;
1051 /* printf("r[%X]",tp->rx_buffs[i]); */
1052 rx_bufs_tmp += 1536;
1053 }
1054
1055 for (i = 0; i < TX_RING_SIZE; i++)
1056 {
1057 tp->tx_buffs[i] = (char *) tx_bufs_tmp;
1058 /* printf("t[%X]",tp->tx_buffs[i]); */
1059 tx_bufs_tmp += 1536;
1060 }
1061
1062 /* software reset */
1063 outb (CR1_SFRST, byCR1);
1064 MIIDelay ();
1065
1066 /* printf ("init ring"); */
1067 rhine_init_ring (nic);
1068 /*write TD RD Descriptor to MAC */
1069 outl (virt_to_bus (tp->rx_ring), dwCurrentRxDescAddr);
1070 outl (virt_to_bus (tp->tx_ring), dwCurrentTxDescAddr);
1071
1072 /* close IMR */
1073 outw (0x0000, byIMR0);
1074
1075 /* set TCR RCR threshold */
1076 outb (0x06, byBCR0);
1077 outb (0x00, byBCR1);
1078 outb (0x2c, byRCR);
1079 outb (0x60, byTCR);
1080 /* Set Fulldupex */
1081 FDXFlag = QueryAuto (ioaddr);
1082 if (FDXFlag == 1)
1083 {
1084 outb (CFGD_CFDX, byCFGD);
1085 outw (CR_FDX, byCR0);
1086 }
1087
1088 /* KICK NIC to WORK */
1089 CRbak = inw (byCR0);
1090 CRbak = CRbak & 0xFFFB; /* not CR_STOP */
1091 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0);
1092
1093 /*set IMR to work */
1094 outw (IMRShadow, byIMR0);
1095 }
1096
1097 static int
rhine_poll(struct nic * nic)1098 rhine_poll (struct nic *nic)
1099 {
1100 struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
1101 int rxstatus, good = 0;;
1102
1103 if (tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit == 0)
1104 {
1105 rxstatus = tp->rx_ring[tp->cur_rx].rx_status.lw;
1106 if ((rxstatus & 0x0300) != 0x0300)
1107 {
1108 printf("rhine_poll: bad status\n");
1109 }
1110 else if (rxstatus & (RSR_ABNORMAL))
1111 {
1112 printf ("rxerr[%X]\n", rxstatus);
1113 }
1114 else
1115 good = 1;
1116
1117 if (good)
1118 {
1119 nic->packetlen = tp->rx_ring[tp->cur_rx].rx_status.bits.frame_length;
1120 memcpy (nic->packet, tp->rx_buffs[tp->cur_rx], nic->packetlen);
1121 /* printf ("Packet RXed\n"); */
1122 }
1123 tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit = 1;
1124 tp->cur_rx++;
1125 tp->cur_rx = tp->cur_rx % RX_RING_SIZE;
1126 }
1127 return good;
1128 }
1129
1130 static void
rhine_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)1131 rhine_transmit (struct nic *nic,
1132 const char *d, unsigned int t, unsigned int s, const char *p)
1133 {
1134 struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
1135 int ioaddr = tp->ioaddr;
1136 int entry;
1137 unsigned char CR1bak;
1138
1139 /*printf ("rhine_transmit\n"); */
1140 /* setup ethernet header */
1141
1142
1143 /* Calculate the next Tx descriptor entry. */
1144 entry = tp->cur_tx % TX_RING_SIZE;
1145
1146 memcpy (tp->tx_buffs[entry], d, ETH_ALEN); /* dst */
1147 memcpy (tp->tx_buffs[entry] + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
1148 *((char *) tp->tx_buffs[entry] + 12) = t >> 8; /* type */
1149 *((char *) tp->tx_buffs[entry] + 13) = t;
1150 memcpy (tp->tx_buffs[entry] + ETH_HLEN, p, s);
1151 s += ETH_HLEN;
1152 while (s < ETH_ZLEN)
1153 *((char *) tp->tx_buffs[entry] + ETH_HLEN + (s++)) = 0;
1154
1155 tp->tx_ring[entry].tx_ctrl.bits.tx_buf_size = ETH_HLEN + s;
1156
1157 tp->tx_ring[entry].tx_status.bits.own_bit = 1;
1158
1159
1160 CR1bak = inb (byCR1);
1161
1162 CR1bak = CR1bak | CR1_TDMD1;
1163 /*printf("tdsw=[%X]",tp->tx_ring[entry].tx_status.lw); */
1164 /*printf("tdcw=[%X]",tp->tx_ring[entry].tx_ctrl.lw); */
1165 /*printf("tdbuf1=[%X]",tp->tx_ring[entry].buf_addr_1); */
1166 /*printf("tdbuf2=[%X]",tp->tx_ring[entry].buf_addr_2); */
1167 /*printf("td1=[%X]",inl(dwCurrentTDSE0)); */
1168 /*printf("td2=[%X]",inl(dwCurrentTDSE1)); */
1169 /*printf("td3=[%X]",inl(dwCurrentTDSE2)); */
1170 /*printf("td4=[%X]",inl(dwCurrentTDSE3)); */
1171
1172 outb (CR1bak, byCR1);
1173 tp->cur_tx++;
1174
1175 /*outw(IMRShadow,byIMR0); */
1176 /*dev_kfree_skb(tp->tx_skbuff[entry], FREE_WRITE); */
1177 /*tp->tx_skbuff[entry] = 0; */
1178 }
1179
1180 /* EOF via-rhine.c */
1181