1 #include "hw/hw.h"
2 #include "hw/boards.h"
3
cpu_save(QEMUFile * f,void * opaque)4 void cpu_save(QEMUFile *f, void *opaque)
5 {
6 int i;
7 CPUARMState *env = (CPUARMState *)opaque;
8
9 for (i = 0; i < 16; i++) {
10 qemu_put_be32(f, env->regs[i]);
11 }
12 qemu_put_be32(f, cpsr_read(env));
13 qemu_put_be32(f, env->spsr);
14 for (i = 0; i < 6; i++) {
15 qemu_put_be32(f, env->banked_spsr[i]);
16 qemu_put_be32(f, env->banked_r13[i]);
17 qemu_put_be32(f, env->banked_r14[i]);
18 }
19 for (i = 0; i < 5; i++) {
20 qemu_put_be32(f, env->usr_regs[i]);
21 qemu_put_be32(f, env->fiq_regs[i]);
22 }
23 qemu_put_be32(f, env->cp15.c0_cpuid);
24 qemu_put_be32(f, env->cp15.c0_cachetype);
25 qemu_put_be32(f, env->cp15.c1_sys);
26 qemu_put_be32(f, env->cp15.c1_coproc);
27 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
28 qemu_put_be32(f, env->cp15.c2_base0);
29 qemu_put_be32(f, env->cp15.c2_base1);
30 qemu_put_be32(f, env->cp15.c2_mask);
31 qemu_put_be32(f, env->cp15.c2_data);
32 qemu_put_be32(f, env->cp15.c2_insn);
33 qemu_put_be32(f, env->cp15.c3);
34 qemu_put_be32(f, env->cp15.c5_insn);
35 qemu_put_be32(f, env->cp15.c5_data);
36 for (i = 0; i < 8; i++) {
37 qemu_put_be32(f, env->cp15.c6_region[i]);
38 }
39 qemu_put_be32(f, env->cp15.c6_insn);
40 qemu_put_be32(f, env->cp15.c6_data);
41 qemu_put_be32(f, env->cp15.c9_insn);
42 qemu_put_be32(f, env->cp15.c9_data);
43 qemu_put_be32(f, env->cp15.c13_fcse);
44 qemu_put_be32(f, env->cp15.c13_context);
45 qemu_put_be32(f, env->cp15.c13_tls1);
46 qemu_put_be32(f, env->cp15.c13_tls2);
47 qemu_put_be32(f, env->cp15.c13_tls3);
48 qemu_put_be32(f, env->cp15.c15_cpar);
49
50 qemu_put_be32(f, env->features);
51
52 if (arm_feature(env, ARM_FEATURE_VFP)) {
53 for (i = 0; i < 16; i++) {
54 CPU_DoubleU u;
55 u.d = env->vfp.regs[i];
56 qemu_put_be32(f, u.l.upper);
57 qemu_put_be32(f, u.l.lower);
58 }
59 for (i = 0; i < 16; i++) {
60 qemu_put_be32(f, env->vfp.xregs[i]);
61 }
62
63 /* TODO: Should use proper FPSCR access functions. */
64 qemu_put_be32(f, env->vfp.vec_len);
65 qemu_put_be32(f, env->vfp.vec_stride);
66
67 if (arm_feature(env, ARM_FEATURE_VFP3)) {
68 for (i = 16; i < 32; i++) {
69 CPU_DoubleU u;
70 u.d = env->vfp.regs[i];
71 qemu_put_be32(f, u.l.upper);
72 qemu_put_be32(f, u.l.lower);
73 }
74 }
75 }
76
77 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
78 for (i = 0; i < 16; i++) {
79 qemu_put_be64(f, env->iwmmxt.regs[i]);
80 }
81 for (i = 0; i < 16; i++) {
82 qemu_put_be32(f, env->iwmmxt.cregs[i]);
83 }
84 }
85
86 if (arm_feature(env, ARM_FEATURE_M)) {
87 qemu_put_be32(f, env->v7m.other_sp);
88 qemu_put_be32(f, env->v7m.vecbase);
89 qemu_put_be32(f, env->v7m.basepri);
90 qemu_put_be32(f, env->v7m.control);
91 qemu_put_be32(f, env->v7m.current_sp);
92 qemu_put_be32(f, env->v7m.exception);
93 }
94 }
95
cpu_load(QEMUFile * f,void * opaque,int version_id)96 int cpu_load(QEMUFile *f, void *opaque, int version_id)
97 {
98 CPUARMState *env = (CPUARMState *)opaque;
99 int i;
100
101 if (version_id != CPU_SAVE_VERSION)
102 return -EINVAL;
103
104 for (i = 0; i < 16; i++) {
105 env->regs[i] = qemu_get_be32(f);
106 }
107 cpsr_write(env, qemu_get_be32(f), 0xffffffff);
108 env->spsr = qemu_get_be32(f);
109 for (i = 0; i < 6; i++) {
110 env->banked_spsr[i] = qemu_get_be32(f);
111 env->banked_r13[i] = qemu_get_be32(f);
112 env->banked_r14[i] = qemu_get_be32(f);
113 }
114 for (i = 0; i < 5; i++) {
115 env->usr_regs[i] = qemu_get_be32(f);
116 env->fiq_regs[i] = qemu_get_be32(f);
117 }
118 env->cp15.c0_cpuid = qemu_get_be32(f);
119 env->cp15.c0_cachetype = qemu_get_be32(f);
120 env->cp15.c1_sys = qemu_get_be32(f);
121 env->cp15.c1_coproc = qemu_get_be32(f);
122 env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
123 env->cp15.c2_base0 = qemu_get_be32(f);
124 env->cp15.c2_base1 = qemu_get_be32(f);
125 env->cp15.c2_mask = qemu_get_be32(f);
126 env->cp15.c2_data = qemu_get_be32(f);
127 env->cp15.c2_insn = qemu_get_be32(f);
128 env->cp15.c3 = qemu_get_be32(f);
129 env->cp15.c5_insn = qemu_get_be32(f);
130 env->cp15.c5_data = qemu_get_be32(f);
131 for (i = 0; i < 8; i++) {
132 env->cp15.c6_region[i] = qemu_get_be32(f);
133 }
134 env->cp15.c6_insn = qemu_get_be32(f);
135 env->cp15.c6_data = qemu_get_be32(f);
136 env->cp15.c9_insn = qemu_get_be32(f);
137 env->cp15.c9_data = qemu_get_be32(f);
138 env->cp15.c13_fcse = qemu_get_be32(f);
139 env->cp15.c13_context = qemu_get_be32(f);
140 env->cp15.c13_tls1 = qemu_get_be32(f);
141 env->cp15.c13_tls2 = qemu_get_be32(f);
142 env->cp15.c13_tls3 = qemu_get_be32(f);
143 env->cp15.c15_cpar = qemu_get_be32(f);
144
145 env->features = qemu_get_be32(f);
146
147 if (arm_feature(env, ARM_FEATURE_VFP)) {
148 for (i = 0; i < 16; i++) {
149 CPU_DoubleU u;
150 u.l.upper = qemu_get_be32(f);
151 u.l.lower = qemu_get_be32(f);
152 env->vfp.regs[i] = u.d;
153 }
154 for (i = 0; i < 16; i++) {
155 env->vfp.xregs[i] = qemu_get_be32(f);
156 }
157
158 /* TODO: Should use proper FPSCR access functions. */
159 env->vfp.vec_len = qemu_get_be32(f);
160 env->vfp.vec_stride = qemu_get_be32(f);
161
162 if (arm_feature(env, ARM_FEATURE_VFP3)) {
163 for (i = 0; i < 16; i++) {
164 CPU_DoubleU u;
165 u.l.upper = qemu_get_be32(f);
166 u.l.lower = qemu_get_be32(f);
167 env->vfp.regs[i] = u.d;
168 }
169 }
170 }
171
172 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
173 for (i = 0; i < 16; i++) {
174 env->iwmmxt.regs[i] = qemu_get_be64(f);
175 }
176 for (i = 0; i < 16; i++) {
177 env->iwmmxt.cregs[i] = qemu_get_be32(f);
178 }
179 }
180
181 if (arm_feature(env, ARM_FEATURE_M)) {
182 env->v7m.other_sp = qemu_get_be32(f);
183 env->v7m.vecbase = qemu_get_be32(f);
184 env->v7m.basepri = qemu_get_be32(f);
185 env->v7m.control = qemu_get_be32(f);
186 env->v7m.current_sp = qemu_get_be32(f);
187 env->v7m.exception = qemu_get_be32(f);
188 }
189
190 return 0;
191 }
192