1 /*
2 * SdioDrv.c
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <mach/hardware.h>
26 #include <linux/i2c/twl4030.h>
27 #include <mach/board.h>
28 #include <linux/errno.h>
29 #include <linux/clk.h>
30 #include <mach/clock.h>
31 #include <mach/dma.h>
32 #include <mach/io.h>
33 #include <mach/resource.h>
34 typedef void *TI_HANDLE;
35 #include "host_platform.h"
36 #include "SdioDrvDbg.h"
37 #include "SdioDrv.h"
38
39 /* #define TI_SDIO_DEBUG */
40
41 #ifndef CONFIG_MMC_EMBEDDED_SDIO
42
43 #define SDIOWQ_NAME "sdio_wq"
44
45 /*
46 * HSMMC Address and DMA Settings
47 */
48 static unsigned long TIWLAN_MMC_CONTROLLER = 2; /* MMC3 */
49 static unsigned long TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE;
50 #define TIWLAN_MMC_CONTROLLER_BASE_SIZE 512
51 #define TIWLAN_MMC_MAX_DMA 8192
52 static unsigned long TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX;
53 static unsigned long TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX;
54 static unsigned long OMAP_MMC_IRQ = INT_MMC3_IRQ;
55
56 #define OMAP_MMC_MASTER_CLOCK 96000000
57 /*
58 * HSMMC Host Controller Registers
59 */
60 #define OMAP_HSMMC_SYSCONFIG 0x0010
61 #define OMAP_HSMMC_SYSSTATUS 0x0014
62 #define OMAP_HSMMC_CSRE 0x0024
63 #define OMAP_HSMMC_SYSTEST 0x0028
64 #define OMAP_HSMMC_CON 0x002C
65 #define OMAP_HSMMC_BLK 0x0104
66 #define OMAP_HSMMC_ARG 0x0108
67 #define OMAP_HSMMC_CMD 0x010C
68 #define OMAP_HSMMC_RSP10 0x0110
69 #define OMAP_HSMMC_RSP32 0x0114
70 #define OMAP_HSMMC_RSP54 0x0118
71 #define OMAP_HSMMC_RSP76 0x011C
72 #define OMAP_HSMMC_DATA 0x0120
73 #define OMAP_HSMMC_PSTATE 0x0124
74 #define OMAP_HSMMC_HCTL 0x0128
75 #define OMAP_HSMMC_SYSCTL 0x012C
76 #define OMAP_HSMMC_STAT 0x0130
77 #define OMAP_HSMMC_IE 0x0134
78 #define OMAP_HSMMC_ISE 0x0138
79 #define OMAP_HSMMC_AC12 0x013C
80 #define OMAP_HSMMC_CAPA 0x0140
81 #define OMAP_HSMMC_CUR_CAPA 0x0148
82 #define OMAP_HSMMC_REV 0x01FC
83
84 #define VS18 (1 << 26)
85 #define VS30 (1 << 25)
86 #define SRA (1 << 24)
87 #define SDVS18 (0x5 << 9)
88 #define SDVS30 (0x6 << 9)
89 #define SDVSCLR 0xFFFFF1FF
90 #define SDVSDET 0x00000400
91 #define SIDLE_MODE (0x2 << 3)
92 #define AUTOIDLE 0x1
93 #define SDBP (1 << 8)
94 #define DTO 0xE
95 #define ICE 0x1
96 #define ICS 0x2
97 #define CEN (1 << 2)
98 #define CLKD_MASK 0x0000FFC0
99 #define IE_EN_MASK 0x317F0137
100 #define INIT_STREAM (1 << 1)
101 #define DP_SELECT (1 << 21)
102 #define DDIR (1 << 4)
103 #define DMA_EN 0x1
104 #define MSBS (1 << 5)
105 #define BCE (1 << 1)
106 #define ONE_BIT (~(0x2))
107 #define EIGHT_BIT (~(0x20))
108 #define CC 0x1
109 #define TC 0x02
110 #define OD 0x1
111 #define BRW 0x400
112 #define BRR 0x800
113 #define BRE (1 << 11)
114 #define BWE (1 << 10)
115 #define SBGR (1 << 16)
116 #define CT (1 << 17)
117 #define SDIO_READ (1 << 31)
118 #define SDIO_BLKMODE (1 << 27)
119 #define OMAP_HSMMC_ERR (1 << 15) /* Any error */
120 #define OMAP_HSMMC_CMD_TIMEOUT (1 << 16) /* Com mand response time-out */
121 #define OMAP_HSMMC_DATA_TIMEOUT (1 << 20) /* Data response time-out */
122 #define OMAP_HSMMC_CMD_CRC (1 << 17) /* Command CRC error */
123 #define OMAP_HSMMC_DATA_CRC (1 << 21) /* Date CRC error */
124 #define OMAP_HSMMC_CARD_ERR (1 << 28) /* Card ERR */
125 #define OMAP_HSMMC_STAT_CLEAR 0xFFFFFFFF
126 #define INIT_STREAM_CMD 0x00000000
127 #define INT_CLEAR 0x00000000
128 #define BLK_CLEAR 0x00000000
129
130 /* SCM CONTROL_DEVCONF1 MMC1 overwrite but */
131
132 #define MMC1_ACTIVE_OVERWRITE (1 << 31)
133
134 #define sdio_blkmode_regaddr 0x2000
135 #define sdio_blkmode_mask 0xFF00
136
137 #define IO_RW_DIRECT_MASK 0xF000FF00
138 #define IO_RW_DIRECT_ARG_MASK 0x80001A00
139
140 #define RMASK (MMC_RSP_MASK | MMC_RSP_CRC)
141 #define MMC_TIMEOUT_MS 100 /*on the new 2430 it was 20, i changed back to 100*//* obc */
142 #define MMCA_VSN_4 4
143
144 #define VMMC1_DEV_GRP 0x27
145 #define P1_DEV_GRP 0x20
146 #define VMMC1_DEDICATED 0x2A
147 #define VSEL_3V 0x02
148 #define VSEL_18V 0x00
149 #define PBIAS_3V 0x03
150 #define PBIAS_18V 0x02
151 #define PBIAS_LITE 0x04A0
152 #define PBIAS_CLR 0x00
153
154 #define OMAP_MMC_REGS_BASE IO_ADDRESS(TIWLAN_MMC_CONTROLLER_BASE_ADDR)
155
156 /*
157 * MMC Host controller read/write API's.
158 */
159 #define OMAP_HSMMC_READ_OFFSET(offset) (__raw_readl((OMAP_MMC_REGS_BASE) + (offset)))
160 #define OMAP_HSMMC_READ(reg) (__raw_readl((OMAP_MMC_REGS_BASE) + OMAP_HSMMC_##reg))
161 #define OMAP_HSMMC_WRITE(reg, val) (__raw_writel((val), (OMAP_MMC_REGS_BASE) + OMAP_HSMMC_##reg))
162
163 #define OMAP_HSMMC_SEND_COMMAND(cmd, arg) do \
164 { \
165 OMAP_HSMMC_WRITE(ARG, arg); \
166 OMAP_HSMMC_WRITE(CMD, cmd); \
167 } while (0)
168
169 #define OMAP_HSMMC_CMD52_WRITE ((SD_IO_RW_DIRECT << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16))
170 #define OMAP_HSMMC_CMD52_READ (((SD_IO_RW_DIRECT << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) | DDIR)
171 #define OMAP_HSMMC_CMD53_WRITE (((SD_IO_RW_EXTENDED << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) | DP_SELECT)
172 #define OMAP_HSMMC_CMD53_READ (((SD_IO_RW_EXTENDED << 24) | (OMAP_HSMMC_CMD_SHORT_RESPONSE << 16)) | DP_SELECT | DDIR)
173 #define OMAP_HSMMC_CMD53_READ_DMA (OMAP_HSMMC_CMD53_READ | DMA_EN)
174 #define OMAP_HSMMC_CMD53_WRITE_DMA (OMAP_HSMMC_CMD53_WRITE | DMA_EN)
175
176 /* Macros to build commands 52 and 53 in format according to SDIO spec */
177 #define SDIO_CMD52_READ(v1,v2,v3,v4) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_RAWFLAG(v3)| SDIO_ADDRREG(v4))
178 #define SDIO_CMD52_WRITE(v1,v2,v3,v4,v5) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_RAWFLAG(v3)| SDIO_ADDRREG(v4)|(v5))
179 #define SDIO_CMD53_READ(v1,v2,v3,v4,v5,v6) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_BLKM(v3)| SDIO_OPCODE(v4)|SDIO_ADDRREG(v5)|(v6&0x1ff))
180 #define SDIO_CMD53_WRITE(v1,v2,v3,v4,v5,v6) (SDIO_RWFLAG(v1)|SDIO_FUNCN(v2)|SDIO_BLKM(v3)| SDIO_OPCODE(v4)|SDIO_ADDRREG(v5)|(v6&0x1ff))
181
182 #define SDIODRV_MAX_LOOPS 50000
183
184 #define VMMC2_DEV_GRP 0x2B
185 #define VMMC2_DEDICATED 0x2E
186 #define VSEL_S2_18V 0x05
187 #define LDO_CLR 0x00
188 #define VSEL_S2_CLR 0x40
189 #define GPIO_0_BIT_POS 1 << 0
190 #define GPIO_1_BIT_POS 1 << 1
191 #define VSIM_DEV_GRP 0x37
192 #define VSIM_DEDICATED 0x3A
193 #define TWL4030_MODULE_PM_RECIEVER 0x13
194
195 typedef struct OMAP3430_sdiodrv
196 {
197 struct clk *fclk, *iclk, *dbclk;
198 int ifclks_enabled;
199 spinlock_t clk_lock;
200 int dma_tx_channel;
201 int dma_rx_channel;
202 int irq;
203 void (*BusTxnCB)(void* BusTxnHandle, int status);
204 void* BusTxnHandle;
205 unsigned int uBlkSize;
206 unsigned int uBlkSizeShift;
207 char *dma_buffer;
208 void *async_buffer;
209 unsigned int async_length;
210 int async_status;
211 int (*wlanDrvIf_pm_resume)(void);
212 int (*wlanDrvIf_pm_suspend)(void);
213 struct device *dev;
214 dma_addr_t dma_read_addr;
215 size_t dma_read_size;
216 dma_addr_t dma_write_addr;
217 size_t dma_write_size;
218 struct workqueue_struct *sdio_wq; /* Work Queue */
219 struct work_struct sdiodrv_work;
220 } OMAP3430_sdiodrv_t;
221
222 struct omap_hsmmc_regs {
223 u32 hctl;
224 u32 capa;
225 u32 sysconfig;
226 u32 ise;
227 u32 ie;
228 u32 con;
229 u32 sysctl;
230 };
231 static struct omap_hsmmc_regs hsmmc_ctx;
232
233 #define SDIO_DRIVER_NAME "TIWLAN_SDIO"
234
235 module_param(g_sdio_debug_level, int, 0644);
236 MODULE_PARM_DESC(g_sdio_debug_level, "debug level");
237 int g_sdio_debug_level = SDIO_DEBUGLEVEL_ERR;
238 EXPORT_SYMBOL(g_sdio_debug_level);
239
240 OMAP3430_sdiodrv_t g_drv;
241
242 static int sdiodrv_dma_on = 0;
243 static int sdiodrv_irq_requested = 0;
244 static int sdiodrv_iclk_got = 0;
245 static int sdiodrv_fclk_got = 0;
246
247 int sdioDrv_clk_enable(void);
248 void sdioDrv_clk_disable(void);
249 static void sdioDrv_hsmmc_save_ctx(void);
250 static void sdioDrv_hsmmc_restore_ctx(void);
251
252 #ifndef TI_SDIO_STANDALONE
sdio_init(int sdcnum)253 void sdio_init( int sdcnum )
254 {
255 if( sdcnum <= 0 )
256 return;
257 TIWLAN_MMC_CONTROLLER = sdcnum - 1;
258 if( sdcnum == 2 ) {
259 TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC2_BASE;
260 TIWLAN_MMC_DMA_TX = OMAP24XX_DMA_MMC2_TX;
261 TIWLAN_MMC_DMA_RX = OMAP24XX_DMA_MMC2_RX;
262 OMAP_MMC_IRQ = INT_MMC2_IRQ;
263 }
264 else if( sdcnum == 3 ) {
265 TIWLAN_MMC_CONTROLLER_BASE_ADDR = OMAP_HSMMC3_BASE;
266 TIWLAN_MMC_DMA_TX = OMAP34XX_DMA_MMC3_TX;
267 TIWLAN_MMC_DMA_RX = OMAP34XX_DMA_MMC3_RX;
268 OMAP_MMC_IRQ = INT_MMC3_IRQ;
269 }
270 }
271 #endif
272
sdioDrv_hsmmc_save_ctx(void)273 static void sdioDrv_hsmmc_save_ctx(void)
274 {
275 /* MMC : context save */
276 hsmmc_ctx.hctl = OMAP_HSMMC_READ(HCTL);
277 hsmmc_ctx.capa = OMAP_HSMMC_READ(CAPA);
278 hsmmc_ctx.sysconfig = OMAP_HSMMC_READ(SYSCONFIG);
279 hsmmc_ctx.ise = OMAP_HSMMC_READ(ISE);
280 hsmmc_ctx.ie = OMAP_HSMMC_READ(IE);
281 hsmmc_ctx.con = OMAP_HSMMC_READ(CON);
282 hsmmc_ctx.sysctl = OMAP_HSMMC_READ(SYSCTL);
283 OMAP_HSMMC_WRITE(ISE, 0);
284 OMAP_HSMMC_WRITE(IE, 0);
285 }
286
sdioDrv_hsmmc_restore_ctx(void)287 static void sdioDrv_hsmmc_restore_ctx(void)
288 {
289 /* MMC : context restore */
290 OMAP_HSMMC_WRITE(HCTL, hsmmc_ctx.hctl);
291 OMAP_HSMMC_WRITE(CAPA, hsmmc_ctx.capa);
292 OMAP_HSMMC_WRITE(SYSCONFIG, hsmmc_ctx.sysconfig);
293 OMAP_HSMMC_WRITE(CON, hsmmc_ctx.con);
294 OMAP_HSMMC_WRITE(ISE, hsmmc_ctx.ise);
295 OMAP_HSMMC_WRITE(IE, hsmmc_ctx.ie);
296 OMAP_HSMMC_WRITE(SYSCTL, hsmmc_ctx.sysctl);
297 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDBP);
298 }
299
sdiodrv_task(struct work_struct * unused)300 void sdiodrv_task(struct work_struct *unused)
301 {
302 PDEBUG("sdiodrv_tasklet()\n");
303
304 if (g_drv.dma_read_addr != 0) {
305 dma_unmap_single(g_drv.dev, g_drv.dma_read_addr, g_drv.dma_read_size, DMA_FROM_DEVICE);
306 g_drv.dma_read_addr = 0;
307 g_drv.dma_read_size = 0;
308 }
309
310 if (g_drv.dma_write_addr != 0) {
311 dma_unmap_single(g_drv.dev, g_drv.dma_write_addr, g_drv.dma_write_size, DMA_TO_DEVICE);
312 g_drv.dma_write_addr = 0;
313 g_drv.dma_write_size = 0;
314 }
315
316 if (g_drv.async_buffer) {
317 memcpy(g_drv.async_buffer, g_drv.dma_buffer, g_drv.async_length);
318 g_drv.async_buffer = NULL;
319 }
320
321 if (g_drv.BusTxnCB != NULL) {
322 g_drv.BusTxnCB(g_drv.BusTxnHandle, g_drv.async_status);
323 }
324 }
325
sdiodrv_irq(int irq,void * drv)326 irqreturn_t sdiodrv_irq(int irq, void *drv)
327 {
328 int status;
329
330 PDEBUG("sdiodrv_irq()\n");
331
332 status = OMAP_HSMMC_READ(STAT);
333 OMAP_HSMMC_WRITE(ISE, 0);
334 g_drv.async_status = status & (OMAP_HSMMC_ERR);
335 if (g_drv.async_status) {
336 PERR("sdiodrv_irq: ERROR in STAT = 0x%x\n", status);
337 }
338 queue_work(g_drv.sdio_wq, &g_drv.sdiodrv_work);
339 return IRQ_HANDLED;
340 }
341
sdiodrv_dma_read_cb(int lch,u16 ch_status,void * data)342 void sdiodrv_dma_read_cb(int lch, u16 ch_status, void *data)
343 {
344 PDEBUG("sdiodrv_dma_read_cb() channel=%d status=0x%x\n", lch, (int)ch_status);
345
346 g_drv.async_status = ch_status & (1 << 7);
347
348 queue_work(g_drv.sdio_wq, &g_drv.sdiodrv_work);
349 }
350
sdiodrv_dma_write_cb(int lch,u16 ch_status,void * data)351 void sdiodrv_dma_write_cb(int lch, u16 ch_status, void *data)
352 {
353 }
354
sdiodrv_dma_init(void)355 int sdiodrv_dma_init(void)
356 {
357 int rc;
358
359 rc = omap_request_dma(TIWLAN_MMC_DMA_TX, "SDIO WRITE", sdiodrv_dma_write_cb, &g_drv, &g_drv.dma_tx_channel);
360 if (rc != 0) {
361 PERR("sdiodrv_dma_init() omap_request_dma(TIWLAN_MMC_DMA_TX) FAILED\n");
362 goto out;
363 }
364
365 rc = omap_request_dma(TIWLAN_MMC_DMA_RX, "SDIO READ", sdiodrv_dma_read_cb, &g_drv, &g_drv.dma_rx_channel);
366 if (rc != 0) {
367 PERR("sdiodrv_dma_init() omap_request_dma(TIWLAN_MMC_DMA_RX) FAILED\n");
368 goto freetx;
369 }
370
371 omap_set_dma_src_params(g_drv.dma_rx_channel,
372 0, // src_port is only for OMAP1
373 OMAP_DMA_AMODE_CONSTANT,
374 (TIWLAN_MMC_CONTROLLER_BASE_ADDR) + OMAP_HSMMC_DATA, 0, 0);
375
376 omap_set_dma_dest_params(g_drv.dma_tx_channel,
377 0, // dest_port is only for OMAP1
378 OMAP_DMA_AMODE_CONSTANT,
379 (TIWLAN_MMC_CONTROLLER_BASE_ADDR) + OMAP_HSMMC_DATA, 0, 0);
380
381 if ((g_drv.dma_buffer = kmalloc(TIWLAN_MMC_MAX_DMA, GFP_ATOMIC|GFP_DMA)) == NULL) {
382 rc = -ENOMEM;
383 goto freerx;
384 }
385
386 return 0;
387
388 freerx:
389 omap_free_dma(g_drv.dma_rx_channel);
390 freetx:
391 omap_free_dma(g_drv.dma_tx_channel);
392 out:
393 return rc;
394 }
395
sdiodrv_dma_shutdown(void)396 void sdiodrv_dma_shutdown(void)
397 {
398 omap_free_dma(g_drv.dma_tx_channel);
399 omap_free_dma(g_drv.dma_rx_channel);
400 if (g_drv.dma_buffer) {
401 kfree(g_drv.dma_buffer);
402 g_drv.dma_buffer = NULL;
403 }
404 } /* sdiodrv_dma_shutdown() */
405
sdiodrv_poll_status(u32 reg_offset,u32 stat,unsigned int msecs)406 static u32 sdiodrv_poll_status(u32 reg_offset, u32 stat, unsigned int msecs)
407 {
408 u32 status=0, loops=0;
409
410 do
411 {
412 status = OMAP_HSMMC_READ_OFFSET(reg_offset);
413 if(( status & stat))
414 {
415 break;
416 }
417 } while (loops++ < SDIODRV_MAX_LOOPS);
418
419 return status;
420 } /* sdiodrv_poll_status */
421
dumpreg(void)422 void dumpreg(void)
423 {
424 printk(KERN_ERR "\n MMCHS_SYSCONFIG for mmc3 = %x ", omap_readl( 0x480AD010 ));
425 printk(KERN_ERR "\n MMCHS_SYSSTATUS for mmc3 = %x ", omap_readl( 0x480AD014 ));
426 printk(KERN_ERR "\n MMCHS_CSRE for mmc3 = %x ", omap_readl( 0x480AD024 ));
427 printk(KERN_ERR "\n MMCHS_SYSTEST for mmc3 = %x ", omap_readl( 0x480AD028 ));
428 printk(KERN_ERR "\n MMCHS_CON for mmc3 = %x ", omap_readl( 0x480AD02C ));
429 printk(KERN_ERR "\n MMCHS_PWCNT for mmc3 = %x ", omap_readl( 0x480AD030 ));
430 printk(KERN_ERR "\n MMCHS_BLK for mmc3 = %x ", omap_readl( 0x480AD104 ));
431 printk(KERN_ERR "\n MMCHS_ARG for mmc3 = %x ", omap_readl( 0x480AD108 ));
432 printk(KERN_ERR "\n MMCHS_CMD for mmc3 = %x ", omap_readl( 0x480AD10C ));
433 printk(KERN_ERR "\n MMCHS_RSP10 for mmc3 = %x ", omap_readl( 0x480AD110 ));
434 printk(KERN_ERR "\n MMCHS_RSP32 for mmc3 = %x ", omap_readl( 0x480AD114 ));
435 printk(KERN_ERR "\n MMCHS_RSP54 for mmc3 = %x ", omap_readl( 0x480AD118 ));
436 printk(KERN_ERR "\n MMCHS_RSP76 for mmc3 = %x ", omap_readl( 0x480AD11C ));
437 printk(KERN_ERR "\n MMCHS_DATA for mmc3 = %x ", omap_readl( 0x480AD120 ));
438 printk(KERN_ERR "\n MMCHS_PSTATE for mmc3 = %x ", omap_readl( 0x480AD124 ));
439 printk(KERN_ERR "\n MMCHS_HCTL for mmc3 = %x ", omap_readl( 0x480AD128 ));
440 printk(KERN_ERR "\n MMCHS_SYSCTL for mmc3 = %x ", omap_readl( 0x480AD12C ));
441 printk(KERN_ERR "\n MMCHS_STAT for mmc3 = %x ", omap_readl( 0x480AD130 ));
442 printk(KERN_ERR "\n MMCHS_IE for mmc3 = %x ", omap_readl( 0x480AD134 ));
443 printk(KERN_ERR "\n MMCHS_ISE for mmc3 = %x ", omap_readl( 0x480AD138 ));
444 printk(KERN_ERR "\n MMCHS_AC12 for mmc3 = %x ", omap_readl( 0x480AD13C ));
445 printk(KERN_ERR "\n MMCHS_CAPA for mmc3 = %x ", omap_readl( 0x480AD140 ));
446 printk(KERN_ERR "\n MMCHS_CUR_CAPA for mmc3 = %x ", omap_readl( 0x480AD148 ));
447 }
448
449 //cmd flow p. 3609 obc
sdiodrv_send_command(u32 cmdreg,u32 cmdarg)450 static int sdiodrv_send_command(u32 cmdreg, u32 cmdarg)
451 {
452 OMAP_HSMMC_WRITE(STAT, OMAP_HSMMC_STAT_CLEAR);
453 OMAP_HSMMC_SEND_COMMAND(cmdreg, cmdarg);
454
455 return sdiodrv_poll_status(OMAP_HSMMC_STAT, CC, MMC_TIMEOUT_MS);
456 } /* sdiodrv_send_command() */
457
458 /*
459 * Disable clock to the card
460 */
OMAP3430_mmc_stop_clock(void)461 static void OMAP3430_mmc_stop_clock(void)
462 {
463 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) & ~CEN);
464 if ((OMAP_HSMMC_READ(SYSCTL) & CEN) != 0x0)
465 {
466 PERR("MMC clock not stoped, clock freq can not be altered\n");
467 }
468 } /* OMAP3430_mmc_stop_clock */
469
470 /*
471 * Reset the SD system
472 */
OMAP3430_mmc_reset(void)473 int OMAP3430_mmc_reset(void)
474 {
475 int status, loops=0;
476 //p. 3598 - need to set SOFTRESET to 0x1 0bc
477 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | SRA);
478 while ((status = OMAP_HSMMC_READ(SYSCTL) & SRA) && loops++ < SDIODRV_MAX_LOOPS);
479 if (status & SRA)
480 {
481 PERR("OMAP3430_mmc_reset() MMC reset FAILED!! status=0x%x\n",status);
482 }
483
484 return status;
485
486 } /* OMAP3430_mmc_reset */
487
488 //p. 3611
OMAP3430_mmc_set_clock(unsigned int clock,OMAP3430_sdiodrv_t * host)489 static void OMAP3430_mmc_set_clock(unsigned int clock, OMAP3430_sdiodrv_t *host)
490 {
491 u16 dsor = 0;
492 unsigned long regVal;
493 int status;
494
495 PDEBUG("OMAP3430_mmc_set_clock(%d)\n",clock);
496 if (clock) {
497 /* Enable MMC_SD_CLK */
498 dsor = OMAP_MMC_MASTER_CLOCK / clock;
499 if (dsor < 1) {
500 dsor = 1;
501 }
502 if (OMAP_MMC_MASTER_CLOCK / dsor > clock) {
503 dsor++;
504 }
505 if (dsor > 250) {
506 dsor = 250;
507 }
508 }
509 OMAP3430_mmc_stop_clock();
510 regVal = OMAP_HSMMC_READ(SYSCTL);
511 regVal = regVal & ~(CLKD_MASK);//p. 3652
512 regVal = regVal | (dsor << 6);
513 regVal = regVal | (DTO << 16);//data timeout
514 OMAP_HSMMC_WRITE(SYSCTL, regVal);
515 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | ICE);//internal clock enable. obc not mentioned in the spec
516 /*
517 * wait till the the clock is stable (ICS) bit is set
518 */
519 status = sdiodrv_poll_status(OMAP_HSMMC_SYSCTL, ICS, MMC_TIMEOUT_MS);
520 if(!(status & ICS)) {
521 PERR("OMAP3430_mmc_set_clock() clock not stable!! status=0x%x\n",status);
522 }
523 /*
524 * Enable clock to the card
525 */
526 OMAP_HSMMC_WRITE(SYSCTL, OMAP_HSMMC_READ(SYSCTL) | CEN);
527
528 } /* OMAP3430_mmc_set_clock() */
529
sdiodrv_free_resources(void)530 static void sdiodrv_free_resources(void)
531 {
532 if(g_drv.ifclks_enabled) {
533 sdioDrv_clk_disable();
534 }
535
536 if (sdiodrv_fclk_got) {
537 clk_put(g_drv.fclk);
538 sdiodrv_fclk_got = 0;
539 }
540
541 if (sdiodrv_iclk_got) {
542 clk_put(g_drv.iclk);
543 sdiodrv_iclk_got = 0;
544 }
545
546 if (sdiodrv_irq_requested) {
547 free_irq(OMAP_MMC_IRQ, &g_drv);
548 sdiodrv_irq_requested = 0;
549 }
550
551 if (sdiodrv_dma_on) {
552 sdiodrv_dma_shutdown();
553 sdiodrv_dma_on = 0;
554 }
555 }
556
sdioDrv_InitHw(void)557 int sdioDrv_InitHw(void)
558 {
559 return 0;
560 } /* sdiodrv_init */
561
sdiodrv_shutdown(void)562 void sdiodrv_shutdown(void)
563 {
564 PDEBUG("entering %s()\n" , __FUNCTION__ );
565
566 sdiodrv_free_resources();
567
568 PDEBUG("exiting %s\n", __FUNCTION__);
569 } /* sdiodrv_shutdown() */
570
sdiodrv_send_data_xfer_commad(u32 cmd,u32 cmdarg,int length,u32 buffer_enable_status,unsigned int bBlkMode)571 static int sdiodrv_send_data_xfer_commad(u32 cmd, u32 cmdarg, int length, u32 buffer_enable_status, unsigned int bBlkMode)
572 {
573 int status;
574
575 PDEBUG("%s() writing CMD 0x%x ARG 0x%x\n",__FUNCTION__, cmd, cmdarg);
576
577 /* block mode */
578 if(bBlkMode) {
579 /*
580 * Bits 31:16 of BLK reg: NBLK Blocks count for current transfer.
581 * in case of Block MOde the lenght is treated here as number of blocks
582 * (and not as a length).
583 * Bits 11:0 of BLK reg: BLEN Transfer Block Size. in case of block mode set that field to block size.
584 */
585 OMAP_HSMMC_WRITE(BLK, (length << 16) | (g_drv.uBlkSize << 0));
586
587 /*
588 * In CMD reg:
589 * BCE: Block Count Enable
590 * MSBS: Multi/Single block select
591 */
592 cmd |= MSBS | BCE ;
593 } else {
594 OMAP_HSMMC_WRITE(BLK, length);
595 }
596
597 status = sdiodrv_send_command(cmd, cmdarg);
598 if(!(status & CC)) {
599 PERR("sdiodrv_send_data_xfer_commad() SDIO Command error! STAT = 0x%x\n", status);
600 return 0;
601 }
602 PDEBUG("%s() length = %d(%dw) BLK = 0x%x\n",
603 __FUNCTION__, length,((length + 3) >> 2), OMAP_HSMMC_READ(BLK));
604
605 return sdiodrv_poll_status(OMAP_HSMMC_PSTATE, buffer_enable_status, MMC_TIMEOUT_MS);
606
607 } /* sdiodrv_send_data_xfer_commad() */
608
sdiodrv_data_xfer_sync(u32 cmd,u32 cmdarg,void * data,int length,u32 buffer_enable_status)609 int sdiodrv_data_xfer_sync(u32 cmd, u32 cmdarg, void *data, int length, u32 buffer_enable_status)
610 {
611 u32 buf_start, buf_end, data32;
612 int status;
613
614 status = sdiodrv_send_data_xfer_commad(cmd, cmdarg, length, buffer_enable_status, 0);
615 if(!(status & buffer_enable_status))
616 {
617 PERR("sdiodrv_data_xfer_sync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x\n",
618 length, OMAP_HSMMC_READ(BLK), status);
619 return -1;
620 }
621 buf_end = (u32)data+(u32)length;
622
623 //obc need to check BRE/BWE every time, see p. 3605
624 /*
625 * Read loop
626 */
627 if (buffer_enable_status == BRE)
628 {
629 if (((u32)data & 3) == 0) /* 4 bytes aligned */
630 {
631 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long))
632 {
633 *((unsigned long*)(data)) = OMAP_HSMMC_READ(DATA);
634 }
635 }
636 else /* 2 bytes aligned */
637 {
638 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long))
639 {
640 data32 = OMAP_HSMMC_READ(DATA);
641 *((unsigned short *)data) = (unsigned short)data32;
642 *((unsigned short *)data + 1) = (unsigned short)(data32 >> 16);
643 }
644 }
645 }
646 /*
647 * Write loop
648 */
649 else
650 {
651 if (((u32)data & 3) == 0) /* 4 bytes aligned */
652 {
653 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long))
654 {
655 OMAP_HSMMC_WRITE(DATA,*((unsigned long*)(data)));
656 }
657 }
658 else /* 2 bytes aligned */
659 {
660 for (buf_start = (u32)data; (u32)data < buf_end; data += sizeof(unsigned long))
661 {
662 OMAP_HSMMC_WRITE(DATA,*((unsigned short*)data) | *((unsigned short*)data+1) << 16 );
663 }
664
665 }
666 }
667 status = sdiodrv_poll_status(OMAP_HSMMC_STAT, TC, MMC_TIMEOUT_MS);
668 if(!(status & TC))
669 {
670 PERR("sdiodrv_data_xfer_sync() transfer error! STAT = 0x%x\n", status);
671 return -1;
672 }
673
674 return 0;
675
676 } /* sdiodrv_data_xfer_sync() */
677
sdioDrv_ConnectBus(void * fCbFunc,void * hCbArg,unsigned int uBlkSizeShift,unsigned int uSdioThreadPriority,unsigned char ** pTxDmaSrcAddr)678 int sdioDrv_ConnectBus (void * fCbFunc,
679 void * hCbArg,
680 unsigned int uBlkSizeShift,
681 unsigned int uSdioThreadPriority,
682 unsigned char **pTxDmaSrcAddr)
683 {
684 g_drv.BusTxnCB = fCbFunc;
685 g_drv.BusTxnHandle = hCbArg;
686 g_drv.uBlkSizeShift = uBlkSizeShift;
687 g_drv.uBlkSize = 1 << uBlkSizeShift;
688
689 INIT_WORK(&g_drv.sdiodrv_work, sdiodrv_task);
690
691 /* Provide the DMA buffer address to the upper layer so it will use it
692 as the transactions host buffer. */
693 if (pTxDmaSrcAddr)
694 {
695 *pTxDmaSrcAddr = g_drv.dma_buffer;
696 }
697 return sdioDrv_InitHw ();
698 }
699
sdioDrv_DisconnectBus(void)700 int sdioDrv_DisconnectBus (void)
701 {
702 sdioDrv_clk_disable(); /* To process Stop command properly */
703 return 0;
704 }
705
706 //p.3609 cmd flow
sdioDrv_ExecuteCmd(unsigned int uCmd,unsigned int uArg,unsigned int uRespType,void * pResponse,unsigned int uLen)707 int sdioDrv_ExecuteCmd (unsigned int uCmd,
708 unsigned int uArg,
709 unsigned int uRespType,
710 void * pResponse,
711 unsigned int uLen)
712 {
713 unsigned int uCmdReg = 0;
714 unsigned int uStatus = 0;
715 unsigned int uResponse = 0;
716
717 PDEBUG("sdioDrv_ExecuteCmd() starting cmd %02x arg %08x\n", (int)uCmd, (int)uArg);
718
719 sdioDrv_clk_enable(); /* To make sure we have clocks enable */
720
721 uCmdReg = (uCmd << 24) | (uRespType << 16) ;
722
723 uStatus = sdiodrv_send_command(uCmdReg, uArg);
724
725 if (!(uStatus & CC))
726 {
727 PERR("sdioDrv_ExecuteCmd() SDIO Command error status = 0x%x\n", uStatus);
728 return -1;
729 }
730 if ((uLen > 0) && (uLen <= 4))/*obc - Len > 4 ? shouldn't read anything ? */
731 {
732 uResponse = OMAP_HSMMC_READ(RSP10);
733 memcpy (pResponse, (char *)&uResponse, uLen);
734 PDEBUG("sdioDrv_ExecuteCmd() response = 0x%x\n", uResponse);
735 }
736 return 0;
737 }
738
739 /*--------------------------------------------------------------------------------------*/
740
sdioDrv_ReadSync(unsigned int uFunc,unsigned int uHwAddr,void * pData,unsigned int uLen,unsigned int bIncAddr,unsigned int bMore)741 int sdioDrv_ReadSync (unsigned int uFunc,
742 unsigned int uHwAddr,
743 void * pData,
744 unsigned int uLen,
745 unsigned int bIncAddr,
746 unsigned int bMore)
747 {
748 unsigned int uCmdArg;
749 int iStatus;
750
751 // printk(KERN_INFO "in sdioDrv_ReadSync\n");
752 uCmdArg = SDIO_CMD53_READ(0, uFunc, 0, bIncAddr, uHwAddr, uLen);
753
754 iStatus = sdiodrv_data_xfer_sync(OMAP_HSMMC_CMD53_READ, uCmdArg, pData, uLen, BRE);
755 if (iStatus != 0) {
756 PERR("sdioDrv_ReadSync() FAILED!!\n");
757 }
758 #ifdef TI_SDIO_DEBUG
759 if (uLen == 1)
760 printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(char *)pData));
761 else if (uLen == 2)
762 printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(short *)pData));
763 else if (uLen == 4)
764 printk(KERN_INFO "R53: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)(*(long *)pData));
765 else
766 printk(KERN_INFO "R53: [0x%x](%u)\n", uHwAddr, uLen);
767 #endif
768 return iStatus;
769 }
770
771 /*--------------------------------------------------------------------------------------*/
sdioDrv_ReadAsync(unsigned int uFunc,unsigned int uHwAddr,void * pData,unsigned int uLen,unsigned int bBlkMode,unsigned int bIncAddr,unsigned int bMore)772 int sdioDrv_ReadAsync (unsigned int uFunc,
773 unsigned int uHwAddr,
774 void * pData,
775 unsigned int uLen,
776 unsigned int bBlkMode,
777 unsigned int bIncAddr,
778 unsigned int bMore)
779 {
780 int iStatus;
781 unsigned int uCmdArg;
782 unsigned int uNumBlks;
783 unsigned int uDmaBlockCount;
784 unsigned int uNumOfElem;
785 void *dma_buffer;
786 dma_addr_t dma_bus_address;
787
788 #ifdef TI_SDIO_DEBUG
789 printk(KERN_INFO "R53: [0x%x](%u) F[%d]\n", uHwAddr, uLen, uFunc);
790 #endif
791
792 //printk(KERN_INFO "in sdioDrv_ReadAsync\n");
793
794 if (bBlkMode)
795 {
796 /* For block mode use number of blocks instead of length in bytes */
797 uNumBlks = uLen >> g_drv.uBlkSizeShift;
798 uDmaBlockCount = uNumBlks;
799 /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */
800 uNumOfElem = g_drv.uBlkSize >> 2;
801 }
802 else
803 {
804 uNumBlks = uLen;
805 uDmaBlockCount = 1;
806 uNumOfElem = (uLen + 3) >> 2;
807 }
808
809 if (((u32)pData & 3) == 0) /* 4 bytes aligned */
810 {
811 dma_buffer = pData;
812 }
813 else /* 2 bytes aligned */
814 {
815 dma_buffer = g_drv.dma_buffer;
816 g_drv.async_buffer = pData;
817 g_drv.async_length = uLen;
818 }
819
820 uCmdArg = SDIO_CMD53_READ(0, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks);
821
822 iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_READ_DMA, uCmdArg, uNumBlks, BRE, bBlkMode);
823
824 if (!(iStatus & BRE))
825 {
826 PERR("sdioDrv_ReadAsync() buffer disabled! length = %d BLK = 0x%x PSTATE = 0x%x, BlkMode = %d\n",
827 uLen, OMAP_HSMMC_READ(BLK), iStatus, bBlkMode);
828 goto err;
829 }
830
831 PDEBUG("sdiodrv_read_async() dma_ch=%d \n",g_drv.dma_rx_channel);
832
833 dma_bus_address = dma_map_single(g_drv.dev, dma_buffer, uLen, DMA_FROM_DEVICE);
834 if (!dma_bus_address) {
835 PERR("sdioDrv_ReadAsync: dma_map_single failed\n");
836 goto err;
837 }
838
839 if (g_drv.dma_read_addr != 0) {
840 printk(KERN_ERR "sdioDrv_ReadAsync: previous DMA op is not finished!\n");
841 BUG();
842 }
843
844 g_drv.dma_read_addr = dma_bus_address;
845 g_drv.dma_read_size = uLen;
846
847 omap_set_dma_dest_params (g_drv.dma_rx_channel,
848 0, // dest_port is only for OMAP1
849 OMAP_DMA_AMODE_POST_INC,
850 dma_bus_address,
851 0, 0);
852
853 omap_set_dma_transfer_params(g_drv.dma_rx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem , uDmaBlockCount , OMAP_DMA_SYNC_FRAME, TIWLAN_MMC_DMA_RX, OMAP_DMA_SRC_SYNC);
854
855 omap_start_dma(g_drv.dma_rx_channel);
856
857 /* Continued at sdiodrv_irq() after DMA transfer is finished */
858 #ifdef TI_SDIO_DEBUG
859 printk(KERN_INFO "R53: [0x%x](%u) (A)\n", uHwAddr, uLen);
860 #endif
861 return 0;
862 err:
863 return -1;
864
865 }
866
867
868 /*--------------------------------------------------------------------------------------*/
869
sdioDrv_WriteSync(unsigned int uFunc,unsigned int uHwAddr,void * pData,unsigned int uLen,unsigned int bIncAddr,unsigned int bMore)870 int sdioDrv_WriteSync (unsigned int uFunc,
871 unsigned int uHwAddr,
872 void * pData,
873 unsigned int uLen,
874 unsigned int bIncAddr,
875 unsigned int bMore)
876 {
877 unsigned int uCmdArg;
878 int iStatus;
879
880 // printk(KERN_INFO "in sdioDrv_WriteSync\n");
881
882 uCmdArg = SDIO_CMD53_WRITE(1, uFunc, 0, bIncAddr, uHwAddr, uLen);
883
884 iStatus = sdiodrv_data_xfer_sync(OMAP_HSMMC_CMD53_WRITE, uCmdArg, pData, uLen, BWE);
885 if (iStatus != 0)
886 {
887 PERR("sdioDrv_WriteSync() FAILED!!\n");
888 }
889 #ifdef TI_SDIO_DEBUG
890 if (uLen == 1)
891 printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(char *)pData));
892 else if (uLen == 2)
893 printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(short *)pData));
894 else if (uLen == 4)
895 printk(KERN_INFO "W53: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)(*(long *)pData));
896 else
897 printk(KERN_INFO "W53: [0x%x](%u)\n", uHwAddr, uLen);
898 #endif
899 return iStatus;
900 }
901
902 /*--------------------------------------------------------------------------------------*/
sdioDrv_WriteAsync(unsigned int uFunc,unsigned int uHwAddr,void * pData,unsigned int uLen,unsigned int bBlkMode,unsigned int bIncAddr,unsigned int bMore)903 int sdioDrv_WriteAsync (unsigned int uFunc,
904 unsigned int uHwAddr,
905 void * pData,
906 unsigned int uLen,
907 unsigned int bBlkMode,
908 unsigned int bIncAddr,
909 unsigned int bMore)
910 {
911 int iStatus;
912 unsigned int uCmdArg;
913 unsigned int uNumBlks;
914 unsigned int uDmaBlockCount;
915 unsigned int uNumOfElem;
916 dma_addr_t dma_bus_address;
917
918 #ifdef TI_SDIO_DEBUG
919 printk(KERN_INFO "W53: [0x%x](%u) F[%d] B[%d] I[%d]\n", uHwAddr, uLen, uFunc, bBlkMode, bIncAddr);
920 #endif
921
922 // printk(KERN_INFO "in sdioDrv_WriteAsync\n");
923 if (bBlkMode)
924 {
925 /* For block mode use number of blocks instead of length in bytes */
926 uNumBlks = uLen >> g_drv.uBlkSizeShift;
927 uDmaBlockCount = uNumBlks;
928 /* due to the DMA config to 32Bit per element (OMAP_DMA_DATA_TYPE_S32) the division is by 4 */
929 uNumOfElem = g_drv.uBlkSize >> 2;
930 }
931 else
932 {
933 uNumBlks = uLen;
934 uDmaBlockCount = 1;
935 uNumOfElem = (uLen + 3) >> 2;
936 }
937
938 uCmdArg = SDIO_CMD53_WRITE(1, uFunc, bBlkMode, bIncAddr, uHwAddr, uNumBlks);
939
940 iStatus = sdiodrv_send_data_xfer_commad(OMAP_HSMMC_CMD53_WRITE_DMA, uCmdArg, uNumBlks, BWE, bBlkMode);
941 if (!(iStatus & BWE))
942 {
943 PERR("sdioDrv_WriteAsync() buffer disabled! length = %d, BLK = 0x%x, Status = 0x%x\n",
944 uLen, OMAP_HSMMC_READ(BLK), iStatus);
945 goto err;
946 }
947
948 OMAP_HSMMC_WRITE(ISE, TC);
949
950 dma_bus_address = dma_map_single(g_drv.dev, pData, uLen, DMA_TO_DEVICE);
951 if (!dma_bus_address) {
952 PERR("sdioDrv_WriteAsync: dma_map_single failed\n");
953 goto err;
954 }
955
956 if (g_drv.dma_write_addr != 0) {
957 PERR("sdioDrv_WriteAsync: previous DMA op is not finished!\n");
958 BUG();
959 }
960
961 g_drv.dma_write_addr = dma_bus_address;
962 g_drv.dma_write_size = uLen;
963
964 omap_set_dma_src_params (g_drv.dma_tx_channel,
965 0, // src_port is only for OMAP1
966 OMAP_DMA_AMODE_POST_INC,
967 dma_bus_address,
968 0, 0);
969
970 omap_set_dma_transfer_params(g_drv.dma_tx_channel, OMAP_DMA_DATA_TYPE_S32, uNumOfElem, uDmaBlockCount, OMAP_DMA_SYNC_FRAME, TIWLAN_MMC_DMA_TX, OMAP_DMA_DST_SYNC);
971
972 omap_start_dma(g_drv.dma_tx_channel);
973
974 /* Continued at sdiodrv_irq() after DMA transfer is finished */
975 return 0;
976 err:
977 return -1;
978 }
979
980 /*--------------------------------------------------------------------------------------*/
981
sdioDrv_ReadSyncBytes(unsigned int uFunc,unsigned int uHwAddr,unsigned char * pData,unsigned int uLen,unsigned int bMore)982 int sdioDrv_ReadSyncBytes (unsigned int uFunc,
983 unsigned int uHwAddr,
984 unsigned char *pData,
985 unsigned int uLen,
986 unsigned int bMore)
987 {
988 unsigned int uCmdArg;
989 unsigned int i;
990 int iStatus;
991
992 for (i = 0; i < uLen; i++) {
993 uCmdArg = SDIO_CMD52_READ(0, uFunc, 0, uHwAddr);
994
995 iStatus = sdiodrv_send_command(OMAP_HSMMC_CMD52_READ, uCmdArg);
996
997 if (!(iStatus & CC)) {
998 PERR("sdioDrv_ReadSyncBytes() SDIO Command error status = 0x%x\n", iStatus);
999 return -1;
1000 }
1001 else {
1002 *pData = (unsigned char)(OMAP_HSMMC_READ(RSP10));
1003 }
1004 #ifdef TI_SDIO_DEBUG
1005 printk(KERN_INFO "R52: [0x%x](%u) = 0x%x\n", uHwAddr, uLen, (unsigned)*pData);
1006 #endif
1007 uHwAddr++;
1008 pData++;
1009 }
1010
1011 return 0;
1012 }
1013
1014 /*--------------------------------------------------------------------------------------*/
1015
sdioDrv_WriteSyncBytes(unsigned int uFunc,unsigned int uHwAddr,unsigned char * pData,unsigned int uLen,unsigned int bMore)1016 int sdioDrv_WriteSyncBytes (unsigned int uFunc,
1017 unsigned int uHwAddr,
1018 unsigned char *pData,
1019 unsigned int uLen,
1020 unsigned int bMore)
1021 {
1022 unsigned int uCmdArg;
1023 unsigned int i;
1024 int iStatus;
1025
1026 for (i = 0; i < uLen; i++) {
1027 #ifdef TI_SDIO_DEBUG
1028 printk(KERN_INFO "W52: [0x%x](%u) < 0x%x\n", uHwAddr, uLen, (unsigned)*pData);
1029 #endif
1030 uCmdArg = SDIO_CMD52_WRITE(1, uFunc, 0, uHwAddr, *pData);
1031
1032 iStatus = sdiodrv_send_command(OMAP_HSMMC_CMD52_WRITE, uCmdArg);
1033 if (!(iStatus & CC)) {
1034 PERR("sdioDrv_WriteSyncBytes() SDIO Command error status = 0x%x\n", iStatus);
1035 return -1;
1036 }
1037 uHwAddr++;
1038 pData++;
1039 }
1040
1041 return 0;
1042 }
1043
sdioDrv_probe(struct platform_device * pdev)1044 static int sdioDrv_probe(struct platform_device *pdev)
1045 {
1046 int rc;
1047 u32 status;
1048 #ifdef SDIO_1_BIT /* see also in SdioAdapter.c */
1049 unsigned long clock_rate = 6000000;
1050 #else
1051 unsigned long clock_rate = 24000000;
1052 #endif
1053
1054 printk(KERN_INFO "TIWLAN SDIO probe: initializing mmc%d device\n", pdev->id + 1);
1055
1056 /* remember device struct for future DMA operations */
1057 g_drv.dev = &pdev->dev;
1058 g_drv.irq = platform_get_irq(pdev, 0);
1059 if (g_drv.irq < 0)
1060 return -ENXIO;
1061
1062 rc= request_irq(OMAP_MMC_IRQ, sdiodrv_irq, 0, SDIO_DRIVER_NAME, &g_drv);
1063 if (rc != 0) {
1064 PERR("sdioDrv_InitHw() - request_irq FAILED!!\n");
1065 return rc;
1066 }
1067 sdiodrv_irq_requested = 1;
1068
1069 rc = sdiodrv_dma_init();
1070 if (rc != 0) {
1071 PERR("sdiodrv_init() - sdiodrv_dma_init FAILED!!\n");
1072 free_irq(OMAP_MMC_IRQ, &g_drv);
1073 return rc;
1074 }
1075 sdiodrv_dma_on = 1;
1076
1077 spin_lock_init(&g_drv.clk_lock);
1078
1079 g_drv.fclk = clk_get(&pdev->dev, "mmchs_fck");
1080 if (IS_ERR(g_drv.fclk)) {
1081 rc = PTR_ERR(g_drv.fclk);
1082 PERR("clk_get(fclk) FAILED !!!\n");
1083 goto err;
1084 }
1085 sdiodrv_fclk_got = 1;
1086
1087 g_drv.iclk = clk_get(&pdev->dev, "mmchs_ick");
1088 if (IS_ERR(g_drv.iclk)) {
1089 rc = PTR_ERR(g_drv.iclk);
1090 PERR("clk_get(iclk) FAILED !!!\n");
1091 goto err;
1092 }
1093 sdiodrv_iclk_got = 1;
1094
1095 rc = sdioDrv_clk_enable();
1096 if (rc) {
1097 PERR("sdioDrv_probe : clk_enable FAILED !!!\n");
1098 goto err;
1099 }
1100
1101 OMAP3430_mmc_reset();
1102
1103 //obc - init sequence p. 3600,3617
1104 /* 1.8V */
1105 OMAP_HSMMC_WRITE(CAPA, OMAP_HSMMC_READ(CAPA) | VS18);
1106 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDVS18);//SDVS fits p. 3650
1107 /* clock gating */
1108 OMAP_HSMMC_WRITE(SYSCONFIG, OMAP_HSMMC_READ(SYSCONFIG) | AUTOIDLE);
1109
1110 /* bus power */
1111 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | SDBP);//SDBP fits p. 3650
1112 /* interrupts */
1113 OMAP_HSMMC_WRITE(ISE, 0);
1114 OMAP_HSMMC_WRITE(IE, IE_EN_MASK);
1115
1116 //p. 3601 suggests moving to the end
1117 OMAP3430_mmc_set_clock(clock_rate, &g_drv);
1118 printk(KERN_INFO "SDIO clock Configuration is now set to %dMhz\n",(int)clock_rate/1000000);
1119
1120 /* Bus width */
1121 #ifdef SDIO_1_BIT /* see also in SdioAdapter.c */
1122 PDEBUG("%s() setting %d data lines\n",__FUNCTION__, 1);
1123 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) & (ONE_BIT));
1124 #else
1125 PDEBUG("%s() setting %d data lines\n",__FUNCTION__, 4);
1126 OMAP_HSMMC_WRITE(HCTL, OMAP_HSMMC_READ(HCTL) | (1 << 1));//DTW 4 bits - p. 3650
1127 #endif
1128
1129 /* send the init sequence. 80 clocks of synchronization in the SDIO */
1130 //doesn't match p. 3601,3617 - obc
1131 OMAP_HSMMC_WRITE( CON, OMAP_HSMMC_READ(CON) | INIT_STREAM);
1132 OMAP_HSMMC_SEND_COMMAND( 0, 0);
1133 status = sdiodrv_poll_status(OMAP_HSMMC_STAT, CC, MMC_TIMEOUT_MS);
1134 if (!(status & CC)) {
1135 PERR("sdioDrv_InitHw() SDIO Command error status = 0x%x\n", status);
1136 rc = -1;
1137 goto err;
1138 }
1139 OMAP_HSMMC_WRITE(CON, OMAP_HSMMC_READ(CON) & ~INIT_STREAM);
1140
1141 return 0;
1142 err:
1143 sdiodrv_free_resources();
1144 return rc;
1145 }
1146
sdioDrv_remove(struct platform_device * pdev)1147 static int sdioDrv_remove(struct platform_device *pdev)
1148 {
1149 printk(KERN_INFO "sdioDrv_remove: calling sdiodrv_shutdown\n");
1150
1151 sdiodrv_shutdown();
1152
1153 return 0;
1154 }
1155
1156 #ifdef CONFIG_PM
sdioDrv_suspend(struct platform_device * pdev,pm_message_t state)1157 static int sdioDrv_suspend(struct platform_device *pdev, pm_message_t state)
1158 {
1159 #if 0
1160 int rc = 0;
1161
1162 /* Tell WLAN driver to suspend, if a suspension function has been registered */
1163 if (g_drv.wlanDrvIf_pm_suspend) {
1164 printk(KERN_INFO "TISDIO: Asking TIWLAN to suspend\n");
1165 rc = g_drv.wlanDrvIf_pm_suspend();
1166 if (rc != 0)
1167 return rc;
1168 }
1169
1170 sdiodrv_shutdown();
1171 #endif
1172 printk(KERN_INFO "TISDIO: sdioDrv is suspending\n");
1173 return 0;
1174 }
1175
1176 /* Routine to resume the MMC device */
sdioDrv_resume(struct platform_device * pdev)1177 static int sdioDrv_resume(struct platform_device *pdev)
1178 {
1179 /* int rc; */
1180
1181 printk(KERN_INFO "TISDIO: sdioDrv is resuming\n");
1182 #if 0
1183 rc = sdioDrv_probe(pdev);
1184 if (rc != 0) {
1185 printk(KERN_ERR "TISDIO: resume error\n");
1186 return rc;
1187 }
1188
1189 if (g_drv.wlanDrvIf_pm_resume) {
1190 printk(KERN_INFO "TISDIO: Asking TIWLAN to resume\n");
1191 return(g_drv.wlanDrvIf_pm_resume());
1192 }
1193 #endif
1194 return 0;
1195 }
1196 #else
1197 #define sdioDrv_suspend NULL
1198 #define sdioDrv_resume NULL
1199 #endif
1200
1201 static struct platform_driver sdioDrv_struct = {
1202 .probe = sdioDrv_probe,
1203 .remove = sdioDrv_remove,
1204 .suspend = sdioDrv_suspend,
1205 .resume = sdioDrv_resume,
1206 .driver = {
1207 .name = SDIO_DRIVER_NAME,
1208 },
1209 };
1210
sdioDrv_register_pm(int (* wlanDrvIf_Start)(void),int (* wlanDrvIf_Stop)(void))1211 void sdioDrv_register_pm(int (*wlanDrvIf_Start)(void),
1212 int (*wlanDrvIf_Stop)(void))
1213 {
1214 g_drv.wlanDrvIf_pm_resume = wlanDrvIf_Start;
1215 g_drv.wlanDrvIf_pm_suspend = wlanDrvIf_Stop;
1216 }
1217
sdioDrv_clk_enable(void)1218 int sdioDrv_clk_enable(void)
1219 {
1220 unsigned long flags;
1221 int ret = 0;
1222
1223 spin_lock_irqsave(&g_drv.clk_lock, flags);
1224 if (g_drv.ifclks_enabled)
1225 goto done;
1226
1227 ret = clk_enable(g_drv.iclk);
1228 if (ret)
1229 goto clk_en_err1;
1230
1231 ret = clk_enable(g_drv.fclk);
1232 if (ret)
1233 goto clk_en_err2;
1234 g_drv.ifclks_enabled = 1;
1235
1236 sdioDrv_hsmmc_restore_ctx();
1237
1238 done:
1239 spin_unlock_irqrestore(&g_drv.clk_lock, flags);
1240 return ret;
1241
1242 clk_en_err2:
1243 clk_disable(g_drv.iclk);
1244 clk_en_err1 :
1245 spin_unlock_irqrestore(&g_drv.clk_lock, flags);
1246 return ret;
1247 }
1248
sdioDrv_clk_disable(void)1249 void sdioDrv_clk_disable(void)
1250 {
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&g_drv.clk_lock, flags);
1254 if (!g_drv.ifclks_enabled)
1255 goto done;
1256
1257 sdioDrv_hsmmc_save_ctx();
1258
1259 clk_disable(g_drv.fclk);
1260 clk_disable(g_drv.iclk);
1261 g_drv.ifclks_enabled = 0;
1262 done:
1263 spin_unlock_irqrestore(&g_drv.clk_lock, flags);
1264 }
1265
1266 #ifdef TI_SDIO_STANDALONE
sdioDrv_init(void)1267 static int __init sdioDrv_init(void)
1268 #else
1269 int __init sdioDrv_init(int sdcnum)
1270 #endif
1271 {
1272 memset(&g_drv, 0, sizeof(g_drv));
1273 memset(&hsmmc_ctx, 0, sizeof(hsmmc_ctx));
1274
1275 printk(KERN_INFO "TIWLAN SDIO init\n");
1276 #ifndef TI_SDIO_STANDALONE
1277 sdio_init( sdcnum );
1278 #endif
1279 g_drv.sdio_wq = create_freezeable_workqueue(SDIOWQ_NAME);
1280 if (!g_drv.sdio_wq) {
1281 printk("TISDIO: Fail to create SDIO WQ\n");
1282 return -EINVAL;
1283 }
1284 /* Register the sdio driver */
1285 return platform_driver_register(&sdioDrv_struct);
1286 }
1287
1288 #ifdef TI_SDIO_STANDALONE
1289 static
1290 #endif
sdioDrv_exit(void)1291 void __exit sdioDrv_exit(void)
1292 {
1293 /* Unregister sdio driver */
1294 platform_driver_unregister(&sdioDrv_struct);
1295 if (g_drv.sdio_wq)
1296 destroy_workqueue(g_drv.sdio_wq);
1297 }
1298
1299 #ifdef TI_SDIO_STANDALONE
1300 module_init(sdioDrv_init);
1301 module_exit(sdioDrv_exit);
1302 #endif
1303
1304 EXPORT_SYMBOL(sdioDrv_ConnectBus);
1305 EXPORT_SYMBOL(sdioDrv_DisconnectBus);
1306 EXPORT_SYMBOL(sdioDrv_ExecuteCmd);
1307 EXPORT_SYMBOL(sdioDrv_ReadSync);
1308 EXPORT_SYMBOL(sdioDrv_WriteSync);
1309 EXPORT_SYMBOL(sdioDrv_ReadAsync);
1310 EXPORT_SYMBOL(sdioDrv_WriteAsync);
1311 EXPORT_SYMBOL(sdioDrv_ReadSyncBytes);
1312 EXPORT_SYMBOL(sdioDrv_WriteSyncBytes);
1313 EXPORT_SYMBOL(sdioDrv_register_pm);
1314 MODULE_DESCRIPTION("TI WLAN SDIO driver");
1315 MODULE_LICENSE("GPL");
1316 MODULE_ALIAS(SDIO_DRIVER_NAME);
1317 MODULE_AUTHOR("Texas Instruments Inc");
1318 #endif
1319