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Searched refs:outw (Results 1 – 25 of 32) sorted by relevance

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/external/grub/netboot/
D3c595.c74 outw(RX_DISABLE, BASE + VX_COMMAND); in t595_reset()
75 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); in t595_reset()
77 outw(TX_DISABLE, BASE + VX_COMMAND); in t595_reset()
78 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); in t595_reset()
80 outw(RX_RESET, BASE + VX_COMMAND); in t595_reset()
82 outw(TX_RESET, BASE + VX_COMMAND); in t595_reset()
84 outw(C_INTR_LATCH, BASE + VX_COMMAND); in t595_reset()
85 outw(SET_RD_0_MASK, BASE + VX_COMMAND); in t595_reset()
86 outw(SET_INTR_MASK, BASE + VX_COMMAND); in t595_reset()
87 outw(SET_RX_FILTER, BASE + VX_COMMAND); in t595_reset()
[all …]
D3c509.c72 outw(RX_DISABLE, BASE + EP_COMMAND); in t509_reset()
73 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND); in t509_reset()
76 outw(TX_DISABLE, BASE + EP_COMMAND); in t509_reset()
77 outw(STOP_TRANSCEIVER, BASE + EP_COMMAND); in t509_reset()
79 outw(RX_RESET, BASE + EP_COMMAND); in t509_reset()
80 outw(TX_RESET, BASE + EP_COMMAND); in t509_reset()
81 outw(C_INTR_LATCH, BASE + EP_COMMAND); in t509_reset()
82 outw(SET_RD_0_MASK, BASE + EP_COMMAND); in t509_reset()
83 outw(SET_INTR_MASK, BASE + EP_COMMAND); in t509_reset()
84 outw(SET_RX_FILTER, BASE + EP_COMMAND); in t509_reset()
[all …]
Dlance.c221 outw(0, ioaddr+LANCE_RESET); in lance_reset()
226 outw(0x2, ioaddr+LANCE_ADDR); in lance_reset()
228 outw(inw(ioaddr+LANCE_BUS_IF) | 0x2, ioaddr+LANCE_BUS_IF); in lance_reset()
237 outw(49, ioaddr+0x12) ; in lance_reset()
249 outw(49, ioaddr+0x12) ; in lance_reset()
250 outw(media, ioaddr+0x16) ; in lance_reset()
251 outw(49, ioaddr+0x12) ; in lance_reset()
274 outw(0x1, ioaddr+LANCE_ADDR); in lance_reset()
276 outw((short)l, ioaddr+LANCE_DATA); in lance_reset()
277 outw(0x2, ioaddr+LANCE_ADDR); in lance_reset()
[all …]
Dcs89x0.c85 outw(portno, eth_nic_base + ADD_PORT); in readreg()
91 outw(portno, eth_nic_base + ADD_PORT); in writereg()
92 outw(value, eth_nic_base + DATA_PORT); in writereg()
248 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT); in send_test_pkt()
249 outw(ETH_ZLEN, eth_nic_base + TX_LEN_PORT); in send_test_pkt()
318 outw(PP_CS8920_ISAINT, eth_nic_base + ADD_PORT); in cs89x0_reset()
323 outw(PP_CS8920_ISAMemB, eth_nic_base + ADD_PORT); in cs89x0_reset()
354 outw(PP_ChipID, eth_nic_base + ADD_PORT); in cs89x0_reset()
380 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT); in cs89x0_transmit()
381 outw(sr, eth_nic_base + TX_LEN_PORT); in cs89x0_transmit()
[all …]
D3c90x.c266 outw(val, ioaddr + regCommandIntStatus_w); in a3c90x_internal_IssueCommand()
306 outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w); in a3c90x_internal_ReadEeprom()
329 outw(0x30, ioaddr + regEepromCommand_0_w); in a3c90x_internal_WriteEepromWord()
333 outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w); in a3c90x_internal_WriteEepromWord()
337 outw(value, ioaddr + regEepromData_0_w); in a3c90x_internal_WriteEepromWord()
338 outw(0x30, ioaddr + regEepromCommand_0_w); in a3c90x_internal_WriteEepromWord()
342 outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w); in a3c90x_internal_WriteEepromWord()
418 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0); in a3c90x_reset()
419 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2); in a3c90x_reset()
420 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4); in a3c90x_reset()
[all …]
Deepro100.c326 outw(EE_ENB, ee_addr); udelay(2); in do_eeprom_cmd()
327 outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2); in do_eeprom_cmd()
332 outw(dataval, ee_addr); udelay(2); in do_eeprom_cmd()
333 outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2); in do_eeprom_cmd()
336 outw(EE_ENB, ee_addr); udelay(2); in do_eeprom_cmd()
339 outw(EE_ENB & ~EE_CS, ee_addr); in do_eeprom_cmd()
387 outw(status & 0xfc00, ioaddr + SCBStatus); in eepro100_transmit()
417 outw(INT_MASK | CU_START, ioaddr + SCBCmd); in eepro100_transmit()
452 outw(INT_MASK | RX_START, ioaddr + SCBCmd); in eepro100_poll()
530 outw(INT_MASK | CU_STATSADDR, ioaddr + SCBCmd); in eepro100_probe()
[all …]
Ddepca.c471 outw(CSR0, DEPCA_ADDR);\
472 outw(STOP, DEPCA_DATA)
503 outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */ in LoadCSRs()
504 outw((u16) (lp.sh_mem & LA_MASK), DEPCA_DATA); in LoadCSRs()
505 outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */ in LoadCSRs()
506 outw((u16) ((lp.sh_mem & LA_MASK) >> 16), DEPCA_DATA); in LoadCSRs()
507 outw(CSR3, DEPCA_ADDR); /* ALE control */ in LoadCSRs()
508 outw(ACON, DEPCA_DATA); in LoadCSRs()
509 outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */ in LoadCSRs()
518 outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */ in InitRestartDepca()
[all …]
Dni5010.c187 outw(0, IE_GP); /* Receive packet at start of buffer */ in reset_receiver()
233 outw(0, IE_GP); /* Seek to beginning of packet */ in ni5010_poll()
258 outw(buf_offs, IE_GP); /* Point GP at start of packet */ in ni5010_transmit()
266 outw(buf_offs, IE_GP); /* Rewrite where packet starts */ in ni5010_transmit()
319 outw(i, IE_GP); in ni5010_probe1()
329 outw(0, IE_GP); /* Point GP at start of packet */ in ni5010_probe1()
332 outw(i << 8, IE_GP); /* Point GP at packet size to be tested */ in ni5010_probe1()
334 outw(0x0, IE_GP); /* Point GP at start of packet */ in ni5010_probe1()
339 outw(0, IE_GP); /* Point GP at start of packet */ in ni5010_probe1()
Deepro.c328 outw(rx_start = (RCV_LOWER_LIMIT << 8), ioaddr + RCV_BAR); in eepro_reset()
329 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), ioaddr + RCV_STOP); in eepro_reset()
331 outw((XMT_LOWER_LIMIT << 8), ioaddr + xmt_bar); in eepro_reset()
355 outw(rcv_car, ioaddr + HOST_ADDRESS_REG); in eepro_poll()
383 outw(rcv_car - 1, ioaddr + RCV_STOP); in eepro_poll()
414 outw(last, ioaddr + HOST_ADDRESS_REG); in eepro_transmit()
415 outw(XMT_CMD, ioaddr + IO_PORT); in eepro_transmit()
416 outw(0, ioaddr + IO_PORT); in eepro_transmit()
417 outw(end, ioaddr + IO_PORT); in eepro_transmit()
418 outw(length, ioaddr + IO_PORT); in eepro_transmit()
[all …]
Drtl8139.c331 outw(0, ioaddr + IntrMask); in rtl_reset()
368 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); in rtl_transmit()
401 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); in rtl_poll()
441 outw(cur_rx - 16, ioaddr + RxBufPtr); in rtl_poll()
445 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); in rtl_poll()
Dnatsemi.c465 outw(0x0001, ioaddr + PGSEL); in natsemi_reset()
466 outw(0x189C, ioaddr + PMDCSR); in natsemi_reset()
467 outw(0x0000, ioaddr + TSTDAT); in natsemi_reset()
468 outw(0x5040, ioaddr + DSPCFG); in natsemi_reset()
469 outw(0x008C, ioaddr + SDCFG); in natsemi_reset()
492 outw(nic->node_addr[i] + (nic->node_addr[i+1] << 8), ioaddr + RxFilterData); in natsemi_init_rxfilter()
Dtiara.c144 outw(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT); in tiara_poll()
177 outw(t, ioaddr + BMPR_MEM_PORT); in tiara_transmit()
183 outw(len | (TMST << 8), ioaddr + BMPR_PKT_LEN); in tiara_transmit()
Dtlan.c333 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead8()
340 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead16()
347 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead32()
354 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite8()
361 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite16()
362 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); in TLan_DioWrite16()
368 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite32()
407 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR ); in TLan_EeSendStart()
446 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR ); in TLan_EeSendByte()
503 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR ); in TLan_EeReceiveByte()
[all …]
Dvia-rhine.c824 outw (ReadMIItmp, wMIIDATA); in WriteMII()
939 outw (CR_FDX, byCR0); in rhine_probe1()
1073 outw (0x0000, byIMR0); in rhine_reset()
1085 outw (CR_FDX, byCR0); in rhine_reset()
1091 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0); in rhine_reset()
1094 outw (IMRShadow, byIMR0); in rhine_reset()
D3c509.h76 #define GO_WINDOW(x) outw(WINDOW_SELECT|(x), BASE+EP_COMMAND)
D3c595.h416 #define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
Dlinux-asm-io.h147 #define outw(val,port) \ macro
/external/openssl/crypto/evp/
De_xcbc_d.c79 DES_cblock outw; member
111 memcpy(&data(ctx)->outw[0],&key[16],8); in desx_cbc_init_key()
124 &data(ctx)->outw, in desx_cbc_cipher()
134 &data(ctx)->outw, in desx_cbc_cipher()
/external/openssl/crypto/des/
Dxcbc_enc.c115 const_DES_cblock *outw, int enc) in DES_xcbc_encrypt() argument
128 in2 = &(*outw)[0]; in DES_xcbc_encrypt()
Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\ argument
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\ argument
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);
Ddes_old.c111 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc) in _ossl_old_des_xcbc_encrypt() argument
114 length, (DES_key_schedule *)schedule, ivec, inw, outw, enc); in _ossl_old_des_xcbc_encrypt()
Ddes.h146 const_DES_cblock *inw,const_DES_cblock *outw,int enc);
/external/openssl/include/openssl/
Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\ argument
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\ argument
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);
Ddes.h146 const_DES_cblock *inw,const_DES_cblock *outw,int enc);
/external/kernel-headers/original/asm-arm/
Dio.h112 #define outw(v,p) __raw_writew((__force __u16) \ macro
133 #define outw_p(val,port) outw((val),(port))

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