1 /* 2 * SDIO Host Controller Spec header file 3 * Register map and definitions for the Standard Host Controller 4 * 5 * Copyright (C) 1999-2010, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * $Id: sdioh.h,v 13.13.18.1.16.3 2009/12/08 22:34:21 Exp $ 26 */ 27 28 #ifndef _SDIOH_H 29 #define _SDIOH_H 30 31 #define SD_SysAddr 0x000 32 #define SD_BlockSize 0x004 33 #define SD_BlockCount 0x006 34 #define SD_Arg0 0x008 35 #define SD_Arg1 0x00A 36 #define SD_TransferMode 0x00C 37 #define SD_Command 0x00E 38 #define SD_Response0 0x010 39 #define SD_Response1 0x012 40 #define SD_Response2 0x014 41 #define SD_Response3 0x016 42 #define SD_Response4 0x018 43 #define SD_Response5 0x01A 44 #define SD_Response6 0x01C 45 #define SD_Response7 0x01E 46 #define SD_BufferDataPort0 0x020 47 #define SD_BufferDataPort1 0x022 48 #define SD_PresentState 0x024 49 #define SD_HostCntrl 0x028 50 #define SD_PwrCntrl 0x029 51 #define SD_BlockGapCntrl 0x02A 52 #define SD_WakeupCntrl 0x02B 53 #define SD_ClockCntrl 0x02C 54 #define SD_TimeoutCntrl 0x02E 55 #define SD_SoftwareReset 0x02F 56 #define SD_IntrStatus 0x030 57 #define SD_ErrorIntrStatus 0x032 58 #define SD_IntrStatusEnable 0x034 59 #define SD_ErrorIntrStatusEnable 0x036 60 #define SD_IntrSignalEnable 0x038 61 #define SD_ErrorIntrSignalEnable 0x03A 62 #define SD_CMD12ErrorStatus 0x03C 63 #define SD_Capabilities 0x040 64 #define SD_Capabilities_Reserved 0x044 65 #define SD_MaxCurCap 0x048 66 #define SD_MaxCurCap_Reserved 0x04C 67 #define SD_ADMA_SysAddr 0x58 68 #define SD_SlotInterruptStatus 0x0FC 69 #define SD_HostControllerVersion 0x0FE 70 71 /* SD specific registers in PCI config space */ 72 #define SD_SlotInfo 0x40 73 74 /* SD_Capabilities reg (0x040) */ 75 #define CAP_TO_CLKFREQ_M BITFIELD_MASK(6) 76 #define CAP_TO_CLKFREQ_S 0 77 #define CAP_TO_CLKUNIT_M BITFIELD_MASK(1) 78 #define CAP_TO_CLKUNIT_S 7 79 #define CAP_BASECLK_M BITFIELD_MASK(6) 80 #define CAP_BASECLK_S 8 81 #define CAP_MAXBLOCK_M BITFIELD_MASK(2) 82 #define CAP_MAXBLOCK_S 16 83 #define CAP_ADMA2_M BITFIELD_MASK(1) 84 #define CAP_ADMA2_S 19 85 #define CAP_ADMA1_M BITFIELD_MASK(1) 86 #define CAP_ADMA1_S 20 87 #define CAP_HIGHSPEED_M BITFIELD_MASK(1) 88 #define CAP_HIGHSPEED_S 21 89 #define CAP_DMA_M BITFIELD_MASK(1) 90 #define CAP_DMA_S 22 91 #define CAP_SUSPEND_M BITFIELD_MASK(1) 92 #define CAP_SUSPEND_S 23 93 #define CAP_VOLT_3_3_M BITFIELD_MASK(1) 94 #define CAP_VOLT_3_3_S 24 95 #define CAP_VOLT_3_0_M BITFIELD_MASK(1) 96 #define CAP_VOLT_3_0_S 25 97 #define CAP_VOLT_1_8_M BITFIELD_MASK(1) 98 #define CAP_VOLT_1_8_S 26 99 #define CAP_64BIT_HOST_M BITFIELD_MASK(1) 100 #define CAP_64BIT_HOST_S 28 101 102 /* SD_MaxCurCap reg (0x048) */ 103 #define CAP_CURR_3_3_M BITFIELD_MASK(8) 104 #define CAP_CURR_3_3_S 0 105 #define CAP_CURR_3_0_M BITFIELD_MASK(8) 106 #define CAP_CURR_3_0_S 8 107 #define CAP_CURR_1_8_M BITFIELD_MASK(8) 108 #define CAP_CURR_1_8_S 16 109 110 /* SD_SysAddr: Offset 0x0000, Size 4 bytes */ 111 112 /* SD_BlockSize: Offset 0x004, Size 2 bytes */ 113 #define BLKSZ_BLKSZ_M BITFIELD_MASK(12) 114 #define BLKSZ_BLKSZ_S 0 115 #define BLKSZ_BNDRY_M BITFIELD_MASK(3) 116 #define BLKSZ_BNDRY_S 12 117 118 /* SD_BlockCount: Offset 0x006, size 2 bytes */ 119 120 /* SD_Arg0: Offset 0x008, size = 4 bytes */ 121 /* SD_TransferMode Offset 0x00C, size = 2 bytes */ 122 #define XFER_DMA_ENABLE_M BITFIELD_MASK(1) 123 #define XFER_DMA_ENABLE_S 0 124 #define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1) 125 #define XFER_BLK_COUNT_EN_S 1 126 #define XFER_CMD_12_EN_M BITFIELD_MASK(1) 127 #define XFER_CMD_12_EN_S 2 128 #define XFER_DATA_DIRECTION_M BITFIELD_MASK(1) 129 #define XFER_DATA_DIRECTION_S 4 130 #define XFER_MULTI_BLOCK_M BITFIELD_MASK(1) 131 #define XFER_MULTI_BLOCK_S 5 132 133 /* SD_Command: Offset 0x00E, size = 2 bytes */ 134 /* resp_type field */ 135 #define RESP_TYPE_NONE 0 136 #define RESP_TYPE_136 1 137 #define RESP_TYPE_48 2 138 #define RESP_TYPE_48_BUSY 3 139 /* type field */ 140 #define CMD_TYPE_NORMAL 0 141 #define CMD_TYPE_SUSPEND 1 142 #define CMD_TYPE_RESUME 2 143 #define CMD_TYPE_ABORT 3 144 145 #define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */ 146 #define CMD_RESP_TYPE_S 0 147 #define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */ 148 #define CMD_CRC_EN_S 3 149 #define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */ 150 #define CMD_INDEX_EN_S 4 151 #define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */ 152 #define CMD_DATA_EN_S 5 153 #define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc 154 */ 155 #define CMD_TYPE_S 6 156 #define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */ 157 #define CMD_INDEX_S 8 158 159 /* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */ 160 /* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */ 161 /* SD_PresentState : Offset 0x024, size = 4 bytes */ 162 #define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */ 163 #define PRES_CMD_INHIBIT_S 0 164 #define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */ 165 #define PRES_DAT_INHIBIT_S 1 166 #define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */ 167 #define PRES_DAT_BUSY_S 2 168 #define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */ 169 #define PRES_PRESENT_RSVD_S 3 170 #define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */ 171 #define PRES_WRITE_ACTIVE_S 8 172 #define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */ 173 #define PRES_READ_ACTIVE_S 9 174 #define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */ 175 #define PRES_WRITE_DATA_RDY_S 10 176 #define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */ 177 #define PRES_READ_DATA_RDY_S 11 178 #define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */ 179 #define PRES_CARD_PRESENT_S 16 180 #define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */ 181 #define PRES_CARD_STABLE_S 17 182 #define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */ 183 #define PRES_CARD_PRESENT_RAW_S 18 184 #define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */ 185 #define PRES_WRITE_ENABLED_S 19 186 #define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */ 187 #define PRES_DAT_SIGNAL_S 20 188 #define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */ 189 #define PRES_CMD_SIGNAL_S 24 190 191 /* SD_HostCntrl: Offset 0x028, size = 1 bytes */ 192 #define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */ 193 #define HOST_LED_S 0 194 #define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */ 195 #define HOST_DATA_WIDTH_S 1 196 #define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */ 197 #define HOST_DMA_SEL_S 3 198 #define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */ 199 #define HOST_HI_SPEED_EN_S 2 200 201 /* misc defines */ 202 #define SD1_MODE 0x1 /* SD Host Cntrlr Spec */ 203 #define SD4_MODE 0x2 /* SD Host Cntrlr Spec */ 204 205 /* SD_PwrCntrl: Offset 0x029, size = 1 bytes */ 206 #define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */ 207 #define PWR_BUS_EN_S 0 208 #define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */ 209 #define PWR_VOLTS_S 1 210 211 /* SD_SoftwareReset: Offset 0x02F, size = 1 byte */ 212 #define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */ 213 #define SW_RESET_ALL_S 0 214 #define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */ 215 #define SW_RESET_CMD_S 1 216 #define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */ 217 #define SW_RESET_DAT_S 2 218 219 /* SD_IntrStatus: Offset 0x030, size = 2 bytes */ 220 /* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */ 221 #define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */ 222 #define INTSTAT_CMD_COMPLETE_S 0 223 #define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1) 224 #define INTSTAT_XFER_COMPLETE_S 1 225 #define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1) 226 #define INTSTAT_BLOCK_GAP_EVENT_S 2 227 #define INTSTAT_DMA_INT_M BITFIELD_MASK(1) 228 #define INTSTAT_DMA_INT_S 3 229 #define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1) 230 #define INTSTAT_BUF_WRITE_READY_S 4 231 #define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1) 232 #define INTSTAT_BUF_READ_READY_S 5 233 #define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1) 234 #define INTSTAT_CARD_INSERTION_S 6 235 #define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1) 236 #define INTSTAT_CARD_REMOVAL_S 7 237 #define INTSTAT_CARD_INT_M BITFIELD_MASK(1) 238 #define INTSTAT_CARD_INT_S 8 239 #define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */ 240 #define INTSTAT_ERROR_INT_S 15 241 242 /* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */ 243 /* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */ 244 #define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1) 245 #define ERRINT_CMD_TIMEOUT_S 0 246 #define ERRINT_CMD_CRC_M BITFIELD_MASK(1) 247 #define ERRINT_CMD_CRC_S 1 248 #define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1) 249 #define ERRINT_CMD_ENDBIT_S 2 250 #define ERRINT_CMD_INDEX_M BITFIELD_MASK(1) 251 #define ERRINT_CMD_INDEX_S 3 252 #define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1) 253 #define ERRINT_DATA_TIMEOUT_S 4 254 #define ERRINT_DATA_CRC_M BITFIELD_MASK(1) 255 #define ERRINT_DATA_CRC_S 5 256 #define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1) 257 #define ERRINT_DATA_ENDBIT_S 6 258 #define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1) 259 #define ERRINT_CURRENT_LIMIT_S 7 260 #define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1) 261 #define ERRINT_AUTO_CMD12_S 8 262 #define ERRINT_VENDOR_M BITFIELD_MASK(4) 263 #define ERRINT_VENDOR_S 12 264 265 /* Also provide definitions in "normal" form to allow combined masks */ 266 #define ERRINT_CMD_TIMEOUT_BIT 0x0001 267 #define ERRINT_CMD_CRC_BIT 0x0002 268 #define ERRINT_CMD_ENDBIT_BIT 0x0004 269 #define ERRINT_CMD_INDEX_BIT 0x0008 270 #define ERRINT_DATA_TIMEOUT_BIT 0x0010 271 #define ERRINT_DATA_CRC_BIT 0x0020 272 #define ERRINT_DATA_ENDBIT_BIT 0x0040 273 #define ERRINT_CURRENT_LIMIT_BIT 0x0080 274 #define ERRINT_AUTO_CMD12_BIT 0x0100 275 276 /* Masks to select CMD vs. DATA errors */ 277 #define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\ 278 ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT) 279 #define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\ 280 ERRINT_DATA_ENDBIT_BIT) 281 #define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS) 282 283 /* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */ 284 /* SD_ClockCntrl : Offset 0x02C , size = bytes */ 285 /* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */ 286 /* SD_IntrStatus : Offset 0x030 , size = bytes */ 287 /* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */ 288 /* SD_IntrStatusEnable : Offset 0x034 , size = bytes */ 289 /* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */ 290 /* SD_IntrSignalEnable : Offset 0x038 , size = bytes */ 291 /* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */ 292 /* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */ 293 /* SD_Capabilities : Offset 0x040 , size = bytes */ 294 /* SD_MaxCurCap : Offset 0x048 , size = bytes */ 295 /* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */ 296 /* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */ 297 /* SD_HostControllerVersion : Offset 0x0FE , size = bytes */ 298 299 #endif /* _SDIOH_H */ 300