388                              AllocationOrder &Order,  in tryAssign()  argument
390   Order.rewind();  in tryAssign()
392   while ((PhysReg = Order.next()))  in tryAssign()
395   if (!PhysReg || Order.isHint(PhysReg))  in tryAssign()
403     if (Order.isHint(Hint)) {  in tryAssign()
421   unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);  in tryAssign()
557                             AllocationOrder &Order,  in tryEvict()  argument
573   Order.rewind();  in tryEvict()
574   while (unsigned PhysReg = Order.next()) {  in tryEvict()
594     if (Order.isHint(PhysReg))  in tryEvict()
948 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,  in tryRegionSplit()  argument
956   Order.rewind();  in tryRegionSplit()
957   while (unsigned PhysReg = Order.next()) {  in tryRegionSplit()
1090 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,  in tryLocalSplit()  argument
1142   Order.rewind();  in tryLocalSplit()
1143   while (unsigned PhysReg = Order.next()) {  in tryLocalSplit()
1278 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,  in trySplit()  argument
1284     return tryLocalSplit(VirtReg, Order, NewVRegs);  in trySplit()
1303     if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))  in trySplit()
1308   unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);  in trySplit()
1335   AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);  in selectOrSplit()  local
1336   if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))  in selectOrSplit()
1347     if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))  in selectOrSplit()
1368   unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);  in selectOrSplit()