Searched refs:ArgRegs (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 193 SmallVectorImpl<unsigned> &ArgRegs,
1538 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument
1560 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
1793 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local
1797 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
1814 ArgRegs.push_back(Arg); in ARMEmitLibcall()
1822 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) in ARMEmitLibcall()
1891 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local
1895 ArgRegs.reserve(CS.arg_size()); in SelectCall()
1926 ArgRegs.push_back(Arg); in SelectCall()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1140 static const unsigned ArgRegs[] = { in LowerCCCArguments() local
1144 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, in LowerCCCArguments()
1145 array_lengthof(ArgRegs)); in LowerCCCArguments()
1146 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1151 for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) { in LowerCCCArguments()
1162 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 658 static const unsigned ArgRegs[] = { in CC_MBlaze_AssignReg() local
663 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_MBlaze_AssignReg()
664 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); in CC_MBlaze_AssignReg()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 305 static const unsigned ArgRegs[] = { in LowerFormalArguments() local
308 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); in LowerFormalArguments()
309 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1524 static const unsigned ArgRegs[] = { in CC_PPC_SVR4_Custom_AlignArgRegs() local
1528 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs()
1530 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs()
1537 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignArgRegs()
1551 static const unsigned ArgRegs[] = { in CC_PPC_SVR4_Custom_AlignFPArgRegs() local
1556 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
1558 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
1562 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC_SVR4_Custom_AlignFPArgRegs()
1563 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 1196 static const unsigned ArgRegs[] = { in LowerFormalArguments() local
1220 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments()
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