• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "mblaze-lower"
16 #include "MBlazeISelLowering.h"
17 #include "MBlazeMachineFunction.h"
18 #include "MBlazeTargetMachine.h"
19 #include "MBlazeTargetObjectFile.h"
20 #include "MBlazeSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 using namespace llvm;
37 
38 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
39                                 CCValAssign::LocInfo &LocInfo,
40                                 ISD::ArgFlagsTy &ArgFlags,
41                                 CCState &State);
42 
getTargetNodeName(unsigned Opcode) const43 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const {
44   switch (Opcode) {
45     case MBlazeISD::JmpLink    : return "MBlazeISD::JmpLink";
46     case MBlazeISD::GPRel      : return "MBlazeISD::GPRel";
47     case MBlazeISD::Wrap       : return "MBlazeISD::Wrap";
48     case MBlazeISD::ICmp       : return "MBlazeISD::ICmp";
49     case MBlazeISD::Ret        : return "MBlazeISD::Ret";
50     case MBlazeISD::Select_CC  : return "MBlazeISD::Select_CC";
51     default                    : return NULL;
52   }
53 }
54 
MBlazeTargetLowering(MBlazeTargetMachine & TM)55 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
56   : TargetLowering(TM, new MBlazeTargetObjectFile()) {
57   Subtarget = &TM.getSubtarget<MBlazeSubtarget>();
58 
59   // MBlaze does not have i1 type, so use i32 for
60   // setcc operations results (slt, sgt, ...).
61   setBooleanContents(ZeroOrOneBooleanContent);
62 
63   // Set up the register classes
64   addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
65   if (Subtarget->hasFPU()) {
66     addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
67     setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
68   }
69 
70   // Floating point operations which are not supported
71   setOperationAction(ISD::FREM,       MVT::f32, Expand);
72   setOperationAction(ISD::FMA,        MVT::f32, Expand);
73   setOperationAction(ISD::UINT_TO_FP, MVT::i8,  Expand);
74   setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
75   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
76   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
77   setOperationAction(ISD::FP_ROUND,   MVT::f32, Expand);
78   setOperationAction(ISD::FP_ROUND,   MVT::f64, Expand);
79   setOperationAction(ISD::FCOPYSIGN,  MVT::f32, Expand);
80   setOperationAction(ISD::FCOPYSIGN,  MVT::f64, Expand);
81   setOperationAction(ISD::FSIN,       MVT::f32, Expand);
82   setOperationAction(ISD::FCOS,       MVT::f32, Expand);
83   setOperationAction(ISD::FPOWI,      MVT::f32, Expand);
84   setOperationAction(ISD::FPOW,       MVT::f32, Expand);
85   setOperationAction(ISD::FLOG,       MVT::f32, Expand);
86   setOperationAction(ISD::FLOG2,      MVT::f32, Expand);
87   setOperationAction(ISD::FLOG10,     MVT::f32, Expand);
88   setOperationAction(ISD::FEXP,       MVT::f32, Expand);
89 
90   // Load extented operations for i1 types must be promoted
91   setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
92   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
93   setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94 
95   // Sign extended loads must be expanded
96   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
97   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
98 
99   // MBlaze has no REM or DIVREM operations.
100   setOperationAction(ISD::UREM,    MVT::i32, Expand);
101   setOperationAction(ISD::SREM,    MVT::i32, Expand);
102   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
103   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
104 
105   // If the processor doesn't support multiply then expand it
106   if (!Subtarget->hasMul()) {
107     setOperationAction(ISD::MUL, MVT::i32, Expand);
108   }
109 
110   // If the processor doesn't support 64-bit multiply then expand
111   if (!Subtarget->hasMul() || !Subtarget->hasMul64()) {
112     setOperationAction(ISD::MULHS, MVT::i32, Expand);
113     setOperationAction(ISD::MULHS, MVT::i64, Expand);
114     setOperationAction(ISD::MULHU, MVT::i32, Expand);
115     setOperationAction(ISD::MULHU, MVT::i64, Expand);
116   }
117 
118   // If the processor doesn't support division then expand
119   if (!Subtarget->hasDiv()) {
120     setOperationAction(ISD::UDIV, MVT::i32, Expand);
121     setOperationAction(ISD::SDIV, MVT::i32, Expand);
122   }
123 
124   // Expand unsupported conversions
125   setOperationAction(ISD::BITCAST, MVT::f32, Expand);
126   setOperationAction(ISD::BITCAST, MVT::i32, Expand);
127 
128   // Expand SELECT_CC
129   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
130 
131   // MBlaze doesn't have MUL_LOHI
132   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
133   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
134   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
135   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
136 
137   // Used by legalize types to correctly generate the setcc result.
138   // Without this, every float setcc comes with a AND/OR with the result,
139   // we don't want this, since the fpcmp result goes to a flag register,
140   // which is used implicitly by brcond and select operations.
141   AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
142   AddPromotedToType(ISD::SELECT, MVT::i1, MVT::i32);
143   AddPromotedToType(ISD::SELECT_CC, MVT::i1, MVT::i32);
144 
145   // MBlaze Custom Operations
146   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
147   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
148   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
149   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
150 
151   // Variable Argument support
152   setOperationAction(ISD::VASTART,            MVT::Other, Custom);
153   setOperationAction(ISD::VAEND,              MVT::Other, Expand);
154   setOperationAction(ISD::VAARG,              MVT::Other, Expand);
155   setOperationAction(ISD::VACOPY,             MVT::Other, Expand);
156 
157 
158   // Operations not directly supported by MBlaze.
159   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Expand);
160   setOperationAction(ISD::BR_JT,              MVT::Other, Expand);
161   setOperationAction(ISD::BR_CC,              MVT::Other, Expand);
162   setOperationAction(ISD::SIGN_EXTEND_INREG,  MVT::i1,    Expand);
163   setOperationAction(ISD::ROTL,               MVT::i32,   Expand);
164   setOperationAction(ISD::ROTR,               MVT::i32,   Expand);
165   setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Expand);
166   setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Expand);
167   setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Expand);
168   setOperationAction(ISD::CTLZ,               MVT::i32,   Expand);
169   setOperationAction(ISD::CTTZ,               MVT::i32,   Expand);
170   setOperationAction(ISD::CTPOP,              MVT::i32,   Expand);
171   setOperationAction(ISD::BSWAP,              MVT::i32,   Expand);
172 
173   // We don't have line number support yet.
174   setOperationAction(ISD::EH_LABEL,          MVT::Other, Expand);
175 
176   // Use the default for now
177   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
178   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
179 
180   // MBlaze doesn't have extending float->double load/store
181   setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
182   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
183 
184   setMinFunctionAlignment(2);
185 
186   setStackPointerRegisterToSaveRestore(MBlaze::R1);
187   computeRegisterProperties();
188 }
189 
getSetCCResultType(EVT VT) const190 MVT::SimpleValueType MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
191   return MVT::i32;
192 }
193 
LowerOperation(SDValue Op,SelectionDAG & DAG) const194 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
195                                              SelectionDAG &DAG) const {
196   switch (Op.getOpcode())
197   {
198     case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
199     case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
200     case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
201     case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
202     case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
203     case ISD::VASTART:            return LowerVASTART(Op, DAG);
204   }
205   return SDValue();
206 }
207 
208 //===----------------------------------------------------------------------===//
209 //  Lower helper functions
210 //===----------------------------------------------------------------------===//
211 MachineBasicBlock*
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * MBB) const212 MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
213                                                   MachineBasicBlock *MBB)
214                                                   const {
215   switch (MI->getOpcode()) {
216   default: assert(false && "Unexpected instr type to insert");
217 
218   case MBlaze::ShiftRL:
219   case MBlaze::ShiftRA:
220   case MBlaze::ShiftL:
221     return EmitCustomShift(MI, MBB);
222 
223   case MBlaze::Select_FCC:
224   case MBlaze::Select_CC:
225     return EmitCustomSelect(MI, MBB);
226 
227   case MBlaze::CAS32:
228   case MBlaze::SWP32:
229   case MBlaze::LAA32:
230   case MBlaze::LAS32:
231   case MBlaze::LAD32:
232   case MBlaze::LAO32:
233   case MBlaze::LAX32:
234   case MBlaze::LAN32:
235     return EmitCustomAtomic(MI, MBB);
236 
237   case MBlaze::MEMBARRIER:
238     // The Microblaze does not need memory barriers. Just delete the pseudo
239     // instruction and finish.
240     MI->eraseFromParent();
241     return MBB;
242   }
243 }
244 
245 MachineBasicBlock*
EmitCustomShift(MachineInstr * MI,MachineBasicBlock * MBB) const246 MBlazeTargetLowering::EmitCustomShift(MachineInstr *MI,
247                                       MachineBasicBlock *MBB) const {
248   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
249   DebugLoc dl = MI->getDebugLoc();
250 
251   // To "insert" a shift left instruction, we actually have to insert a
252   // simple loop.  The incoming instruction knows the destination vreg to
253   // set, the source vreg to operate over and the shift amount.
254   const BasicBlock *LLVM_BB = MBB->getBasicBlock();
255   MachineFunction::iterator It = MBB;
256   ++It;
257 
258   // start:
259   //   andi     samt, samt, 31
260   //   beqid    samt, finish
261   //   add      dst, src, r0
262   // loop:
263   //   addik    samt, samt, -1
264   //   sra      dst, dst
265   //   bneid    samt, loop
266   //   nop
267   // finish:
268   MachineFunction *F = MBB->getParent();
269   MachineRegisterInfo &R = F->getRegInfo();
270   MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
271   MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
272   F->insert(It, loop);
273   F->insert(It, finish);
274 
275   // Update machine-CFG edges by transferring adding all successors and
276   // remaining instructions from the current block to the new block which
277   // will contain the Phi node for the select.
278   finish->splice(finish->begin(), MBB,
279                  llvm::next(MachineBasicBlock::iterator(MI)),
280                  MBB->end());
281   finish->transferSuccessorsAndUpdatePHIs(MBB);
282 
283   // Add the true and fallthrough blocks as its successors.
284   MBB->addSuccessor(loop);
285   MBB->addSuccessor(finish);
286 
287   // Next, add the finish block as a successor of the loop block
288   loop->addSuccessor(finish);
289   loop->addSuccessor(loop);
290 
291   unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
292   BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
293     .addReg(MI->getOperand(2).getReg())
294     .addImm(31);
295 
296   unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
297   BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
298     .addReg(MI->getOperand(1).getReg())
299     .addImm(0);
300 
301   BuildMI(MBB, dl, TII->get(MBlaze::BEQID))
302     .addReg(IAMT)
303     .addMBB(finish);
304 
305   unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
306   unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
307   BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
308     .addReg(IVAL).addMBB(MBB)
309     .addReg(NDST).addMBB(loop);
310 
311   unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
312   unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
313   BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
314     .addReg(IAMT).addMBB(MBB)
315     .addReg(NAMT).addMBB(loop);
316 
317   if (MI->getOpcode() == MBlaze::ShiftL)
318     BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
319   else if (MI->getOpcode() == MBlaze::ShiftRA)
320     BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
321   else if (MI->getOpcode() == MBlaze::ShiftRL)
322     BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
323   else
324     llvm_unreachable("Cannot lower unknown shift instruction");
325 
326   BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
327     .addReg(SAMT)
328     .addImm(-1);
329 
330   BuildMI(loop, dl, TII->get(MBlaze::BNEID))
331     .addReg(NAMT)
332     .addMBB(loop);
333 
334   BuildMI(*finish, finish->begin(), dl,
335           TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
336     .addReg(IVAL).addMBB(MBB)
337     .addReg(NDST).addMBB(loop);
338 
339   // The pseudo instruction is no longer needed so remove it
340   MI->eraseFromParent();
341   return finish;
342 }
343 
344 MachineBasicBlock*
EmitCustomSelect(MachineInstr * MI,MachineBasicBlock * MBB) const345 MBlazeTargetLowering::EmitCustomSelect(MachineInstr *MI,
346                                        MachineBasicBlock *MBB) const {
347   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
348   DebugLoc dl = MI->getDebugLoc();
349 
350   // To "insert" a SELECT_CC instruction, we actually have to insert the
351   // diamond control-flow pattern.  The incoming instruction knows the
352   // destination vreg to set, the condition code register to branch on, the
353   // true/false values to select between, and a branch opcode to use.
354   const BasicBlock *LLVM_BB = MBB->getBasicBlock();
355   MachineFunction::iterator It = MBB;
356   ++It;
357 
358   //  thisMBB:
359   //  ...
360   //   TrueVal = ...
361   //   setcc r1, r2, r3
362   //   bNE   r1, r0, copy1MBB
363   //   fallthrough --> copy0MBB
364   MachineFunction *F = MBB->getParent();
365   MachineBasicBlock *flsBB = F->CreateMachineBasicBlock(LLVM_BB);
366   MachineBasicBlock *dneBB = F->CreateMachineBasicBlock(LLVM_BB);
367 
368   unsigned Opc;
369   switch (MI->getOperand(4).getImm()) {
370   default: llvm_unreachable("Unknown branch condition");
371   case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
372   case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
373   case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
374   case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
375   case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
376   case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
377   }
378 
379   F->insert(It, flsBB);
380   F->insert(It, dneBB);
381 
382   // Transfer the remainder of MBB and its successor edges to dneBB.
383   dneBB->splice(dneBB->begin(), MBB,
384                 llvm::next(MachineBasicBlock::iterator(MI)),
385                 MBB->end());
386   dneBB->transferSuccessorsAndUpdatePHIs(MBB);
387 
388   MBB->addSuccessor(flsBB);
389   MBB->addSuccessor(dneBB);
390   flsBB->addSuccessor(dneBB);
391 
392   BuildMI(MBB, dl, TII->get(Opc))
393     .addReg(MI->getOperand(3).getReg())
394     .addMBB(dneBB);
395 
396   //  sinkMBB:
397   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
398   //  ...
399   //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
400   //  .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
401   //  .addReg(MI->getOperand(2).getReg()).addMBB(BB);
402 
403   BuildMI(*dneBB, dneBB->begin(), dl,
404           TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
405     .addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
406     .addReg(MI->getOperand(1).getReg()).addMBB(MBB);
407 
408   MI->eraseFromParent();   // The pseudo instruction is gone now.
409   return dneBB;
410 }
411 
412 MachineBasicBlock*
EmitCustomAtomic(MachineInstr * MI,MachineBasicBlock * MBB) const413 MBlazeTargetLowering::EmitCustomAtomic(MachineInstr *MI,
414                                        MachineBasicBlock *MBB) const {
415   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
416   DebugLoc dl = MI->getDebugLoc();
417 
418   // All atomic instructions on the Microblaze are implemented using the
419   // load-linked / store-conditional style atomic instruction sequences.
420   // Thus, all operations will look something like the following:
421   //
422   //  start:
423   //    lwx     RV, RP, 0
424   //    <do stuff>
425   //    swx     RV, RP, 0
426   //    addic   RC, R0, 0
427   //    bneid   RC, start
428   //
429   //  exit:
430   //
431   // To "insert" a shift left instruction, we actually have to insert a
432   // simple loop.  The incoming instruction knows the destination vreg to
433   // set, the source vreg to operate over and the shift amount.
434   const BasicBlock *LLVM_BB = MBB->getBasicBlock();
435   MachineFunction::iterator It = MBB;
436   ++It;
437 
438   // start:
439   //   andi     samt, samt, 31
440   //   beqid    samt, finish
441   //   add      dst, src, r0
442   // loop:
443   //   addik    samt, samt, -1
444   //   sra      dst, dst
445   //   bneid    samt, loop
446   //   nop
447   // finish:
448   MachineFunction *F = MBB->getParent();
449   MachineRegisterInfo &R = F->getRegInfo();
450 
451   // Create the start and exit basic blocks for the atomic operation
452   MachineBasicBlock *start = F->CreateMachineBasicBlock(LLVM_BB);
453   MachineBasicBlock *exit = F->CreateMachineBasicBlock(LLVM_BB);
454   F->insert(It, start);
455   F->insert(It, exit);
456 
457   // Update machine-CFG edges by transferring adding all successors and
458   // remaining instructions from the current block to the new block which
459   // will contain the Phi node for the select.
460   exit->splice(exit->begin(), MBB, llvm::next(MachineBasicBlock::iterator(MI)),
461                MBB->end());
462   exit->transferSuccessorsAndUpdatePHIs(MBB);
463 
464   // Add the fallthrough block as its successors.
465   MBB->addSuccessor(start);
466 
467   BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg())
468     .addReg(MI->getOperand(1).getReg())
469     .addReg(MBlaze::R0);
470 
471   MachineBasicBlock *final = start;
472   unsigned finalReg = 0;
473 
474   switch (MI->getOpcode()) {
475   default: llvm_unreachable("Cannot lower unknown atomic instruction!");
476 
477   case MBlaze::SWP32:
478     finalReg = MI->getOperand(2).getReg();
479     start->addSuccessor(exit);
480     start->addSuccessor(start);
481     break;
482 
483   case MBlaze::LAN32:
484   case MBlaze::LAX32:
485   case MBlaze::LAO32:
486   case MBlaze::LAD32:
487   case MBlaze::LAS32:
488   case MBlaze::LAA32: {
489     unsigned opcode = 0;
490     switch (MI->getOpcode()) {
491     default: llvm_unreachable("Cannot lower unknown atomic load!");
492     case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
493     case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
494     case MBlaze::LAD32: opcode = MBlaze::AND; break;
495     case MBlaze::LAO32: opcode = MBlaze::OR; break;
496     case MBlaze::LAX32: opcode = MBlaze::XOR; break;
497     case MBlaze::LAN32: opcode = MBlaze::AND; break;
498     }
499 
500     finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
501     start->addSuccessor(exit);
502     start->addSuccessor(start);
503 
504     BuildMI(start, dl, TII->get(opcode), finalReg)
505       .addReg(MI->getOperand(0).getReg())
506       .addReg(MI->getOperand(2).getReg());
507 
508     if (MI->getOpcode() == MBlaze::LAN32) {
509       unsigned tmp = finalReg;
510       finalReg = R.createVirtualRegister(MBlaze::GPRRegisterClass);
511       BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg)
512         .addReg(tmp)
513         .addImm(-1);
514     }
515     break;
516   }
517 
518   case MBlaze::CAS32: {
519     finalReg = MI->getOperand(3).getReg();
520     final = F->CreateMachineBasicBlock(LLVM_BB);
521 
522     F->insert(It, final);
523     start->addSuccessor(exit);
524     start->addSuccessor(final);
525     final->addSuccessor(exit);
526     final->addSuccessor(start);
527 
528     unsigned CMP = R.createVirtualRegister(MBlaze::GPRRegisterClass);
529     BuildMI(start, dl, TII->get(MBlaze::CMP), CMP)
530       .addReg(MI->getOperand(0).getReg())
531       .addReg(MI->getOperand(2).getReg());
532 
533     BuildMI(start, dl, TII->get(MBlaze::BNEID))
534       .addReg(CMP)
535       .addMBB(exit);
536 
537     final->moveAfter(start);
538     exit->moveAfter(final);
539     break;
540   }
541   }
542 
543   unsigned CHK = R.createVirtualRegister(MBlaze::GPRRegisterClass);
544   BuildMI(final, dl, TII->get(MBlaze::SWX))
545     .addReg(finalReg)
546     .addReg(MI->getOperand(1).getReg())
547     .addReg(MBlaze::R0);
548 
549   BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK)
550     .addReg(MBlaze::R0)
551     .addImm(0);
552 
553   BuildMI(final, dl, TII->get(MBlaze::BNEID))
554     .addReg(CHK)
555     .addMBB(start);
556 
557   // The pseudo instruction is no longer needed so remove it
558   MI->eraseFromParent();
559   return exit;
560 }
561 
562 //===----------------------------------------------------------------------===//
563 //  Misc Lower Operation implementation
564 //===----------------------------------------------------------------------===//
565 //
566 
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const567 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
568                                              SelectionDAG &DAG) const {
569   SDValue LHS = Op.getOperand(0);
570   SDValue RHS = Op.getOperand(1);
571   SDValue TrueVal = Op.getOperand(2);
572   SDValue FalseVal = Op.getOperand(3);
573   DebugLoc dl = Op.getDebugLoc();
574   unsigned Opc;
575 
576   SDValue CompareFlag;
577   if (LHS.getValueType() == MVT::i32) {
578     Opc = MBlazeISD::Select_CC;
579     CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS)
580                     .getValue(1);
581   } else {
582     llvm_unreachable("Cannot lower select_cc with unknown type");
583   }
584 
585   return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
586                      CompareFlag);
587 }
588 
589 SDValue MBlazeTargetLowering::
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const590 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
591   // FIXME there isn't actually debug info here
592   DebugLoc dl = Op.getDebugLoc();
593   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
594   SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
595 
596   return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA);
597 }
598 
599 SDValue MBlazeTargetLowering::
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const600 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
601   llvm_unreachable("TLS not implemented for MicroBlaze.");
602   return SDValue(); // Not reached
603 }
604 
605 SDValue MBlazeTargetLowering::
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const606 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
607   SDValue ResNode;
608   SDValue HiPart;
609   // FIXME there isn't actually debug info here
610   DebugLoc dl = Op.getDebugLoc();
611 
612   EVT PtrVT = Op.getValueType();
613   JumpTableSDNode *JT  = cast<JumpTableSDNode>(Op);
614 
615   SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0);
616   return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI);
617 }
618 
619 SDValue MBlazeTargetLowering::
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const620 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
621   SDValue ResNode;
622   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
623   const Constant *C = N->getConstVal();
624   DebugLoc dl = Op.getDebugLoc();
625 
626   SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
627                                          N->getOffset(), 0);
628   return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
629 }
630 
LowerVASTART(SDValue Op,SelectionDAG & DAG) const631 SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op,
632                                            SelectionDAG &DAG) const {
633   MachineFunction &MF = DAG.getMachineFunction();
634   MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>();
635 
636   DebugLoc dl = Op.getDebugLoc();
637   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
638                                  getPointerTy());
639 
640   // vastart just stores the address of the VarArgsFrameIndex slot into the
641   // memory location argument.
642   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
643   return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
644                       MachinePointerInfo(SV),
645                       false, false, 0);
646 }
647 
648 //===----------------------------------------------------------------------===//
649 //                      Calling Convention Implementation
650 //===----------------------------------------------------------------------===//
651 
652 #include "MBlazeGenCallingConv.inc"
653 
CC_MBlaze_AssignReg(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)654 static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
655                                 CCValAssign::LocInfo &LocInfo,
656                                 ISD::ArgFlagsTy &ArgFlags,
657                                 CCState &State) {
658   static const unsigned ArgRegs[] = {
659     MBlaze::R5, MBlaze::R6, MBlaze::R7,
660     MBlaze::R8, MBlaze::R9, MBlaze::R10
661   };
662 
663   const unsigned NumArgRegs = array_lengthof(ArgRegs);
664   unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs);
665   if (!Reg) return false;
666 
667   unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
668   State.AllocateStack(SizeInBytes, SizeInBytes);
669   State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
670 
671   return true;
672 }
673 
674 //===----------------------------------------------------------------------===//
675 //                  Call Calling Convention Implementation
676 //===----------------------------------------------------------------------===//
677 
678 /// LowerCall - functions arguments are copied from virtual regs to
679 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
680 /// TODO: isVarArg, isTailCall.
681 SDValue MBlazeTargetLowering::
LowerCall(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool & isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const682 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
683           bool isVarArg, bool &isTailCall,
684           const SmallVectorImpl<ISD::OutputArg> &Outs,
685           const SmallVectorImpl<SDValue> &OutVals,
686           const SmallVectorImpl<ISD::InputArg> &Ins,
687           DebugLoc dl, SelectionDAG &DAG,
688           SmallVectorImpl<SDValue> &InVals) const {
689   // MBlaze does not yet support tail call optimization
690   isTailCall = false;
691 
692   // The MBlaze requires stack slots for arguments passed to var arg
693   // functions even if they are passed in registers.
694   bool needsRegArgSlots = isVarArg;
695 
696   MachineFunction &MF = DAG.getMachineFunction();
697   MachineFrameInfo *MFI = MF.getFrameInfo();
698   const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
699 
700   // Analyze operands of the call, assigning locations to each operand.
701   SmallVector<CCValAssign, 16> ArgLocs;
702   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
703 		 getTargetMachine(), ArgLocs, *DAG.getContext());
704   CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
705 
706   // Get a count of how many bytes are to be pushed on the stack.
707   unsigned NumBytes = CCInfo.getNextStackOffset();
708 
709   // Variable argument function calls require a minimum of 24-bytes of stack
710   if (isVarArg && NumBytes < 24) NumBytes = 24;
711 
712   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
713 
714   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
715   SmallVector<SDValue, 8> MemOpChains;
716 
717   // Walk the register/memloc assignments, inserting copies/loads.
718   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
719     CCValAssign &VA = ArgLocs[i];
720     MVT RegVT = VA.getLocVT();
721     SDValue Arg = OutVals[i];
722 
723     // Promote the value if needed.
724     switch (VA.getLocInfo()) {
725     default: llvm_unreachable("Unknown loc info!");
726     case CCValAssign::Full: break;
727     case CCValAssign::SExt:
728       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
729       break;
730     case CCValAssign::ZExt:
731       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
732       break;
733     case CCValAssign::AExt:
734       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
735       break;
736     }
737 
738     // Arguments that can be passed on register must be kept at
739     // RegsToPass vector
740     if (VA.isRegLoc()) {
741       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
742     } else {
743       // Register can't get to this point...
744       assert(VA.isMemLoc());
745 
746       // Since we are alread passing values on the stack we don't
747       // need to worry about creating additional slots for the
748       // values passed via registers.
749       needsRegArgSlots = false;
750 
751       // Create the frame index object for this incoming parameter
752       unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
753       unsigned StackLoc = VA.getLocMemOffset() + 4;
754       int FI = MFI->CreateFixedObject(ArgSize, StackLoc, true);
755 
756       SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
757 
758       // emit ISD::STORE whichs stores the
759       // parameter value to a stack Location
760       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
761                                          MachinePointerInfo(),
762                                          false, false, 0));
763     }
764   }
765 
766   // If we need to reserve stack space for the arguments passed via registers
767   // then create a fixed stack object at the beginning of the stack.
768   if (needsRegArgSlots && TFI.hasReservedCallFrame(MF))
769     MFI->CreateFixedObject(28,0,true);
770 
771   // Transform all store nodes into one single node because all store
772   // nodes are independent of each other.
773   if (!MemOpChains.empty())
774     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
775                         &MemOpChains[0], MemOpChains.size());
776 
777   // Build a sequence of copy-to-reg nodes chained together with token
778   // chain and flag operands which copy the outgoing args into registers.
779   // The InFlag in necessary since all emitted instructions must be
780   // stuck together.
781   SDValue InFlag;
782   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
783     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
784                              RegsToPass[i].second, InFlag);
785     InFlag = Chain.getValue(1);
786   }
787 
788   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
789   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
790   // node so that legalize doesn't hack it.
791   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
792     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
793                                 getPointerTy(), 0, 0);
794   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
795     Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
796                                 getPointerTy(), 0);
797 
798   // MBlazeJmpLink = #chain, #target_address, #opt_in_flags...
799   //             = Chain, Callee, Reg#1, Reg#2, ...
800   //
801   // Returns a chain & a flag for retval copy to use.
802   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
803   SmallVector<SDValue, 8> Ops;
804   Ops.push_back(Chain);
805   Ops.push_back(Callee);
806 
807   // Add argument registers to the end of the list so that they are
808   // known live into the call.
809   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
810     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
811                                   RegsToPass[i].second.getValueType()));
812   }
813 
814   if (InFlag.getNode())
815     Ops.push_back(InFlag);
816 
817   Chain  = DAG.getNode(MBlazeISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
818   InFlag = Chain.getValue(1);
819 
820   // Create the CALLSEQ_END node.
821   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
822                              DAG.getIntPtrConstant(0, true), InFlag);
823   if (!Ins.empty())
824     InFlag = Chain.getValue(1);
825 
826   // Handle result values, copying them out of physregs into vregs that we
827   // return.
828   return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
829                          Ins, dl, DAG, InVals);
830 }
831 
832 /// LowerCallResult - Lower the result values of a call into the
833 /// appropriate copies out of appropriate physical registers.
834 SDValue MBlazeTargetLowering::
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const835 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
836                 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
837                 DebugLoc dl, SelectionDAG &DAG,
838                 SmallVectorImpl<SDValue> &InVals) const {
839   // Assign locations to each value returned by this call.
840   SmallVector<CCValAssign, 16> RVLocs;
841   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
842 		 getTargetMachine(), RVLocs, *DAG.getContext());
843 
844   CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
845 
846   // Copy all of the result registers out of their specified physreg.
847   for (unsigned i = 0; i != RVLocs.size(); ++i) {
848     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
849                                RVLocs[i].getValVT(), InFlag).getValue(1);
850     InFlag = Chain.getValue(2);
851     InVals.push_back(Chain.getValue(0));
852   }
853 
854   return Chain;
855 }
856 
857 //===----------------------------------------------------------------------===//
858 //             Formal Arguments Calling Convention Implementation
859 //===----------------------------------------------------------------------===//
860 
861 /// LowerFormalArguments - transform physical registers into
862 /// virtual registers and generate load operations for
863 /// arguments places on the stack.
864 SDValue MBlazeTargetLowering::
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const865 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
866                      const SmallVectorImpl<ISD::InputArg> &Ins,
867                      DebugLoc dl, SelectionDAG &DAG,
868                      SmallVectorImpl<SDValue> &InVals) const {
869   MachineFunction &MF = DAG.getMachineFunction();
870   MachineFrameInfo *MFI = MF.getFrameInfo();
871   MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
872 
873   unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
874   MBlazeFI->setVarArgsFrameIndex(0);
875 
876   // Used with vargs to acumulate store chains.
877   std::vector<SDValue> OutChains;
878 
879   // Keep track of the last register used for arguments
880   unsigned ArgRegEnd = 0;
881 
882   // Assign locations to all of the incoming arguments.
883   SmallVector<CCValAssign, 16> ArgLocs;
884   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
885 		 getTargetMachine(), ArgLocs, *DAG.getContext());
886 
887   CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze);
888   SDValue StackPtr;
889 
890   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
891     CCValAssign &VA = ArgLocs[i];
892 
893     // Arguments stored on registers
894     if (VA.isRegLoc()) {
895       MVT RegVT = VA.getLocVT();
896       ArgRegEnd = VA.getLocReg();
897       TargetRegisterClass *RC = 0;
898 
899       if (RegVT == MVT::i32)
900         RC = MBlaze::GPRRegisterClass;
901       else if (RegVT == MVT::f32)
902         RC = MBlaze::GPRRegisterClass;
903       else
904         llvm_unreachable("RegVT not supported by LowerFormalArguments");
905 
906       // Transform the arguments stored on
907       // physical registers into virtual ones
908       unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
909       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
910 
911       // If this is an 8 or 16-bit value, it has been passed promoted
912       // to 32 bits.  Insert an assert[sz]ext to capture this, then
913       // truncate to the right size. If if is a floating point value
914       // then convert to the correct type.
915       if (VA.getLocInfo() != CCValAssign::Full) {
916         unsigned Opcode = 0;
917         if (VA.getLocInfo() == CCValAssign::SExt)
918           Opcode = ISD::AssertSext;
919         else if (VA.getLocInfo() == CCValAssign::ZExt)
920           Opcode = ISD::AssertZext;
921         if (Opcode)
922           ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
923                                  DAG.getValueType(VA.getValVT()));
924         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
925       }
926 
927       InVals.push_back(ArgValue);
928     } else { // VA.isRegLoc()
929       // sanity check
930       assert(VA.isMemLoc());
931 
932       // The last argument is not a register
933       ArgRegEnd = 0;
934 
935       // The stack pointer offset is relative to the caller stack frame.
936       // Since the real stack size is unknown here, a negative SPOffset
937       // is used so there's a way to adjust these offsets when the stack
938       // size get known (on EliminateFrameIndex). A dummy SPOffset is
939       // used instead of a direct negative address (which is recorded to
940       // be used on emitPrologue) to avoid mis-calc of the first stack
941       // offset on PEI::calculateFrameObjectOffsets.
942       // Arguments are always 32-bit.
943       unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
944       unsigned StackLoc = VA.getLocMemOffset() + 4;
945       int FI = MFI->CreateFixedObject(ArgSize, 0, true);
946       MBlazeFI->recordLoadArgsFI(FI, -StackLoc);
947       MBlazeFI->recordLiveIn(FI);
948 
949       // Create load nodes to retrieve arguments from the stack
950       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
951       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
952                                    MachinePointerInfo::getFixedStack(FI),
953                                    false, false, 0));
954     }
955   }
956 
957   // To meet ABI, when VARARGS are passed on registers, the registers
958   // must have their values written to the caller stack frame. If the last
959   // argument was placed in the stack, there's no need to save any register.
960   if ((isVarArg) && ArgRegEnd) {
961     if (StackPtr.getNode() == 0)
962       StackPtr = DAG.getRegister(StackReg, getPointerTy());
963 
964     // The last register argument that must be saved is MBlaze::R10
965     TargetRegisterClass *RC = MBlaze::GPRRegisterClass;
966 
967     unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
968     unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1);
969     unsigned End   = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10);
970     unsigned StackLoc = Start - Begin + 1;
971 
972     for (; Start <= End; ++Start, ++StackLoc) {
973       unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
974       unsigned LiveReg = MF.addLiveIn(Reg, RC);
975       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
976 
977       int FI = MFI->CreateFixedObject(4, 0, true);
978       MBlazeFI->recordStoreVarArgsFI(FI, -(StackLoc*4));
979       SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
980       OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
981                                        MachinePointerInfo(),
982                                        false, false, 0));
983 
984       // Record the frame index of the first variable argument
985       // which is a value necessary to VASTART.
986       if (!MBlazeFI->getVarArgsFrameIndex())
987         MBlazeFI->setVarArgsFrameIndex(FI);
988     }
989   }
990 
991   // All stores are grouped in one node to allow the matching between
992   // the size of Ins and InVals. This only happens when on varg functions
993   if (!OutChains.empty()) {
994     OutChains.push_back(Chain);
995     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
996                         &OutChains[0], OutChains.size());
997   }
998 
999   return Chain;
1000 }
1001 
1002 //===----------------------------------------------------------------------===//
1003 //               Return Value Calling Convention Implementation
1004 //===----------------------------------------------------------------------===//
1005 
1006 SDValue MBlazeTargetLowering::
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,DebugLoc dl,SelectionDAG & DAG) const1007 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1008             const SmallVectorImpl<ISD::OutputArg> &Outs,
1009             const SmallVectorImpl<SDValue> &OutVals,
1010             DebugLoc dl, SelectionDAG &DAG) const {
1011   // CCValAssign - represent the assignment of
1012   // the return value to a location
1013   SmallVector<CCValAssign, 16> RVLocs;
1014 
1015   // CCState - Info about the registers and stack slot.
1016   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1017 		 getTargetMachine(), RVLocs, *DAG.getContext());
1018 
1019   // Analize return values.
1020   CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze);
1021 
1022   // If this is the first return lowered for this function, add
1023   // the regs to the liveout set for the function.
1024   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1025     for (unsigned i = 0; i != RVLocs.size(); ++i)
1026       if (RVLocs[i].isRegLoc())
1027         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1028   }
1029 
1030   SDValue Flag;
1031 
1032   // Copy the result values into the output registers.
1033   for (unsigned i = 0; i != RVLocs.size(); ++i) {
1034     CCValAssign &VA = RVLocs[i];
1035     assert(VA.isRegLoc() && "Can only return in registers!");
1036 
1037     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1038                              OutVals[i], Flag);
1039 
1040     // guarantee that all emitted copies are
1041     // stuck together, avoiding something bad
1042     Flag = Chain.getValue(1);
1043   }
1044 
1045   // If this function is using the interrupt_handler calling convention
1046   // then use "rtid r14, 0" otherwise use "rtsd r15, 8"
1047   unsigned Ret = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlazeISD::IRet
1048                                                               : MBlazeISD::Ret;
1049   unsigned Reg = (CallConv == llvm::CallingConv::MBLAZE_INTR) ? MBlaze::R14
1050                                                               : MBlaze::R15;
1051   SDValue DReg = DAG.getRegister(Reg, MVT::i32);
1052 
1053   if (Flag.getNode())
1054     return DAG.getNode(Ret, dl, MVT::Other, Chain, DReg, Flag);
1055 
1056   return DAG.getNode(Ret, dl, MVT::Other, Chain, DReg);
1057 }
1058 
1059 //===----------------------------------------------------------------------===//
1060 //                           MBlaze Inline Assembly Support
1061 //===----------------------------------------------------------------------===//
1062 
1063 /// getConstraintType - Given a constraint letter, return the type of
1064 /// constraint it is for this target.
1065 MBlazeTargetLowering::ConstraintType MBlazeTargetLowering::
getConstraintType(const std::string & Constraint) const1066 getConstraintType(const std::string &Constraint) const
1067 {
1068   // MBlaze specific constrainy
1069   //
1070   // 'd' : An address register. Equivalent to r.
1071   // 'y' : Equivalent to r; retained for
1072   //       backwards compatibility.
1073   // 'f' : Floating Point registers.
1074   if (Constraint.size() == 1) {
1075     switch (Constraint[0]) {
1076       default : break;
1077       case 'd':
1078       case 'y':
1079       case 'f':
1080         return C_RegisterClass;
1081         break;
1082     }
1083   }
1084   return TargetLowering::getConstraintType(Constraint);
1085 }
1086 
1087 /// Examine constraint type and operand type and determine a weight value.
1088 /// This object must already have been set up with the operand type
1089 /// and the current alternative constraint selected.
1090 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const1091 MBlazeTargetLowering::getSingleConstraintMatchWeight(
1092     AsmOperandInfo &info, const char *constraint) const {
1093   ConstraintWeight weight = CW_Invalid;
1094   Value *CallOperandVal = info.CallOperandVal;
1095     // If we don't have a value, we can't do a match,
1096     // but allow it at the lowest weight.
1097   if (CallOperandVal == NULL)
1098     return CW_Default;
1099   Type *type = CallOperandVal->getType();
1100   // Look at the constraint type.
1101   switch (*constraint) {
1102   default:
1103     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1104     break;
1105   case 'd':
1106   case 'y':
1107     if (type->isIntegerTy())
1108       weight = CW_Register;
1109     break;
1110   case 'f':
1111     if (type->isFloatTy())
1112       weight = CW_Register;
1113     break;
1114   }
1115   return weight;
1116 }
1117 
1118 /// Given a register class constraint, like 'r', if this corresponds directly
1119 /// to an LLVM register class, return a register of 0 and the register class
1120 /// pointer.
1121 std::pair<unsigned, const TargetRegisterClass*> MBlazeTargetLowering::
getRegForInlineAsmConstraint(const std::string & Constraint,EVT VT) const1122 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
1123   if (Constraint.size() == 1) {
1124     switch (Constraint[0]) {
1125     case 'r':
1126       return std::make_pair(0U, MBlaze::GPRRegisterClass);
1127       // TODO: These can't possibly be right, but match what was in
1128       // getRegClassForInlineAsmConstraint.
1129     case 'd':
1130     case 'y':
1131     case 'f':
1132       if (VT == MVT::f32)
1133         return std::make_pair(0U, MBlaze::GPRRegisterClass);
1134     }
1135   }
1136   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1137 }
1138 
1139 bool MBlazeTargetLowering::
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const1140 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1141   // The MBlaze target isn't yet aware of offsets.
1142   return false;
1143 }
1144 
isFPImmLegal(const APFloat & Imm,EVT VT) const1145 bool MBlazeTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1146   return VT != MVT::f32;
1147 }
1148