/external/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 164 LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation() 167 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation() 168 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation() 169 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation() 170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation() 171 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation() 172 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation() 173 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation() 174 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation() 175 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation() [all …]
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D | XCoreISelLowering.h | 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 93 SelectionDAG &DAG) const; 115 DebugLoc dl, SelectionDAG &DAG, 123 DebugLoc dl, SelectionDAG &DAG, 128 DebugLoc dl, SelectionDAG &DAG, 130 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 132 SelectionDAG &DAG) const; 135 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 136 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; [all …]
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeDAG.cpp | 52 SelectionDAG &DAG; member in __anonf6dc01730111::SelectionDAGLegalize 73 DAG.TransferDbgValues(From, To); in AddLegalizedOperand() 77 explicit SelectionDAGLegalize(SelectionDAG &DAG); 179 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); in ShuffleWithNarrowerEltType() 193 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); in ShuffleWithNarrowerEltType() 198 DAG(dag) { in SelectionDAGLegalize() 202 pushLastCALLSEQ(DAG.getEntryNode()); in LegalizeDAG() 210 DAG.AssignTopologicalOrder(); in LegalizeDAG() 211 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), in LegalizeDAG() 212 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) in LegalizeDAG() [all …]
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D | LegalizeIntegerTypes.cpp | 37 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); in PromoteIntegerResult() 48 N->dump(&DAG); dbgs() << "\n"; in PromoteIntegerResult() 142 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), in PromoteIntRes_AssertSext() 149 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), in PromoteIntRes_AssertZext() 155 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), in PromoteIntRes_Atomic1() 168 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), in PromoteIntRes_Atomic2() 180 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_BITCAST() 182 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in PromoteIntRes_BITCAST() 194 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST() 198 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST() [all …]
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D | LegalizeTypesGeneric.cpp | 37 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST() 52 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 53 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 59 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 60 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 66 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 67 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 72 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST() 73 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST() 78 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), in ExpandRes_BITCAST() [all …]
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D | SelectionDAGBuilder.cpp | 88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, in getCopyFromParts() argument 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); in getCopyFromParts() 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in getCopyFromParts() 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts() 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, in getCopyFromParts() 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, in getCopyFromParts() 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts() 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts() [all …]
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D | LegalizeVectorTypes.cpp | 36 N->dump(&DAG); in ScalarizeVectorResult() 44 N->dump(&DAG); in ScalarizeVectorResult() 128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), in ScalarizeVecRes_BinOp() 134 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in ScalarizeVecRes_BITCAST() 141 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), in ScalarizeVecRes_CONVERT_RNDSAT() 142 Op0, DAG.getValueType(NewVT), in ScalarizeVecRes_CONVERT_RNDSAT() 143 DAG.getValueType(Op0.getValueType()), in ScalarizeVecRes_CONVERT_RNDSAT() 150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), in ScalarizeVecRes_EXTRACT_SUBVECTOR() 158 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), in ScalarizeVecRes_FP_ROUND() 164 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), in ScalarizeVecRes_FPOWI() [all …]
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D | DAGCombiner.cpp | 59 SelectionDAG &DAG; member in __anon3ce142f50111::DAGCombiner 281 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), in DAGCombiner() 287 SelectionDAG &getDAG() const { return DAG; } in getDAG() 419 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, in GetNegatedExpression() argument 433 return DAG.getConstantFP(V, Op.getValueType()); in GetNegatedExpression() 441 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression() 442 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression() 446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression() 447 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression() 460 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression() [all …]
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D | LegalizeVectorOps.cpp | 36 SelectionDAG& DAG; member in __anond206314c0111::VectorLegalizer 73 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} in VectorLegalizer() 83 DAG.AssignTopologicalOrder(); in Run() 84 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), in Run() 85 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) in Run() 89 SDValue OldRoot = DAG.getRoot(); in Run() 91 DAG.setRoot(LegalizedNodes[OldRoot]); in Run() 96 DAG.RemoveDeadNodes(); in Run() 122 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0); in LegalizeOp() 205 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); in LegalizeOp() [all …]
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/external/llvm/lib/Target/CellSPU/ |
D | SPUISelLowering.cpp | 61 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG, in ExpandLibCall() argument 66 SDValue InChain = DAG.getEntryNode(); in ExpandLibCall() 72 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in ExpandLibCall() 79 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), in ExpandLibCall() 84 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext()); in ExpandLibCall() 89 Callee, Args, DAG, Op.getDebugLoc()); in ExpandLibCall() 544 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { in LowerLOAD() argument 547 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); in LowerLOAD() 554 EVT vecVT = InVT.isVector()? InVT: EVT::getVectorVT(*DAG.getContext(), InVT, in LowerLOAD() 588 rotate = DAG.getConstant(rotamt, MVT::i16); in LowerLOAD() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 85 DebugLoc dl, SelectionDAG &DAG) const { in LowerReturn() 87 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn() 93 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerReturn() 94 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerReturn() 114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn() 128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); in LowerReturn() 129 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); in LowerReturn() 136 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32); in LowerReturn() 139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn() 141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.h | 495 SelectionDAG &DAG) const; 535 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 541 SelectionDAG &DAG) const; 577 const SelectionDAG &DAG, 588 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 608 SelectionDAG &DAG) const; 695 SelectionDAG &DAG) const; 730 DebugLoc dl, SelectionDAG &DAG, 735 DebugLoc dl, SelectionDAG &DAG, 739 DebugLoc dl, SelectionDAG &DAG, [all …]
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D | X86SelectionDAGInfo.cpp | 30 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, in EmitTargetCodeForMemset() argument 57 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); in EmitTargetCodeForMemset() 66 TLI.LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), in EmitTargetCodeForMemset() 69 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, in EmitTargetCodeForMemset() 70 DAG, dl); in EmitTargetCodeForMemset() 110 Count = DAG.getIntPtrConstant(SizeVal); in EmitTargetCodeForMemset() 116 Count = DAG.getIntPtrConstant(SizeVal / UBytes); in EmitTargetCodeForMemset() 120 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), in EmitTargetCodeForMemset() 125 Count = DAG.getIntPtrConstant(SizeVal); in EmitTargetCodeForMemset() 126 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); in EmitTargetCodeForMemset() [all …]
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D | X86ISelLowering.cpp | 60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 66 SelectionDAG &DAG, 71 SelectionDAG &DAG, 74 static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG); 84 SelectionDAG &DAG, in Extract128BitVector() argument 93 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), in Extract128BitVector() 99 return DAG.getNode(ISD::UNDEF, dl, ResultVT); in Extract128BitVector() 113 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); in Extract128BitVector() 115 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in Extract128BitVector() 132 SelectionDAG &DAG, in Insert128BitVector() argument [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.h | 233 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 257 SelectionDAG &DAG) const; 263 SelectionDAG &DAG) const; 269 SelectionDAG &DAG) const; 274 SelectionDAG &DAG) const; 280 SelectionDAG &DAG) const; 285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 291 SelectionDAG &DAG) const; 299 const SelectionDAG &DAG, 333 SelectionDAG &DAG) const; [all …]
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D | PPCISelLowering.cpp | 660 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { in get_VSPLTI_elt() argument 703 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef in get_VSPLTI_elt() 706 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) in get_VSPLTI_elt() 710 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef in get_VSPLTI_elt() 713 return DAG.getTargetConstant(Val, MVT::i32); in get_VSPLTI_elt() 765 return DAG.getTargetConstant(MaskVal, MVT::i32); in get_VSPLTI_elt() 797 SelectionDAG &DAG) const { in SelectAddressRegReg() 817 DAG.ComputeMaskedBits(N.getOperand(0), in SelectAddressRegReg() 823 DAG.ComputeMaskedBits(N.getOperand(1), in SelectAddressRegReg() 845 SelectionDAG &DAG) const { in SelectAddressRegImm() [all …]
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/external/llvm/lib/Target/Alpha/ |
D | AlphaISelLowering.cpp | 188 static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) { in LowerJumpTable() argument 191 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); in LowerJumpTable() 195 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI, in LowerJumpTable() 196 DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); in LowerJumpTable() 197 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi); in LowerJumpTable() 229 DebugLoc dl, SelectionDAG &DAG, in LowerCall() argument 236 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCall() 237 getTargetMachine(), ArgLocs, *DAG.getContext()); in LowerCall() 244 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, in LowerCall() 262 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 1091 DebugLoc dl, SelectionDAG &DAG, in LowerCallResult() argument 1096 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerCallResult() 1097 getTargetMachine(), RVLocs, *DAG.getContext(), Call); in LowerCallResult() 1109 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult() 1114 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult() 1118 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult() 1121 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult() 1122 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult() 1123 DAG.getConstant(0, MVT::i32)); in LowerCallResult() 1126 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult() [all …]
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D | ARMISelLowering.h | 233 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 239 SelectionDAG &DAG) const; 247 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 280 SelectionDAG &DAG) const; 288 SelectionDAG &DAG) const; 294 const SelectionDAG &DAG, 318 SelectionDAG &DAG) const; 371 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 379 SDValue &Root, SelectionDAG &DAG, 385 DebugLoc dl, SelectionDAG &DAG, [all …]
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D | ARMSelectionDAGInfo.cpp | 29 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, in EmitTargetCodeForMemcpy() argument 66 Loads[i] = DAG.getLoad(VT, dl, Chain, in EmitTargetCodeForMemcpy() 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, in EmitTargetCodeForMemcpy() 68 DAG.getConstant(SrcOff, MVT::i32)), in EmitTargetCodeForMemcpy() 74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy() 78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], in EmitTargetCodeForMemcpy() 79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, in EmitTargetCodeForMemcpy() 80 DAG.getConstant(DstOff, MVT::i32)), in EmitTargetCodeForMemcpy() 85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); in EmitTargetCodeForMemcpy() 105 Loads[i] = DAG.getLoad(VT, dl, Chain, in EmitTargetCodeForMemcpy() [all …]
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/external/llvm/lib/Target/Blackfin/ |
D | BlackfinISelLowering.cpp | 144 SelectionDAG &DAG) const { in LowerGlobalAddress() 148 Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32); in LowerGlobalAddress() 149 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op); in LowerGlobalAddress() 153 SelectionDAG &DAG) const { in LowerJumpTable() 157 Op = DAG.getTargetJumpTable(JTI, MVT::i32); in LowerJumpTable() 158 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op); in LowerJumpTable() 166 DebugLoc dl, SelectionDAG &DAG, in LowerFormalArguments() argument 170 MachineFunction &MF = DAG.getMachineFunction(); in LowerFormalArguments() 174 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), in LowerFormalArguments() 175 getTargetMachine(), ArgLocs, *DAG.getContext()); in LowerFormalArguments() [all …]
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 179 SelectionDAG &DAG) const { in LowerOperation() 183 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation() 184 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation() 185 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation() 186 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); in LowerOperation() 187 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation() 188 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation() 189 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation() 190 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation() 191 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); in LowerOperation() [all …]
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D | MSP430ISelLowering.h | 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; 93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 346 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, in PerformADDECombine() argument 352 if (Subtarget->isMips32() && SelectMadd(N, &DAG)) in PerformADDECombine() 358 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, in PerformSUBECombine() argument 364 if (Subtarget->isMips32() && SelectMsub(N, &DAG)) in PerformSUBECombine() 370 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, in PerformDivRemCombine() argument 380 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, in PerformDivRemCombine() 382 SDValue InChain = DAG.getEntryNode(); in PerformDivRemCombine() 387 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, in PerformDivRemCombine() 389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); in PerformDivRemCombine() 396 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, in PerformDivRemCombine() [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 163 SelectionDAG &DAG) const { in LowerOperation() 165 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation() 166 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation() 167 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation() 168 case ISD::JumpTable: return LowerJumpTable(Op, DAG); in LowerOperation() 169 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation() 240 SelectionDAG &DAG, in LowerFormalArguments() argument 249 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); in LowerFormalArguments() 260 DebugLoc dl, SelectionDAG &DAG, in LowerCall() argument 271 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall() [all …]
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