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Searched refs:ECX (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86Subtarget.cpp177 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in AutoDetectSubtargetFeatures() local
186 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
192 if (ECX & 0x1) X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); in AutoDetectSubtargetFeatures()
193 if ((ECX >> 9) & 1) X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3); in AutoDetectSubtargetFeatures()
194 if ((ECX >> 19) & 1) X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41); in AutoDetectSubtargetFeatures()
195 if ((ECX >> 20) & 1) X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42); in AutoDetectSubtargetFeatures()
202 HasCLMUL = IsIntel && ((ECX >> 1) & 0x1); ToggleFeature(X86::FeatureCLMUL); in AutoDetectSubtargetFeatures()
203 HasFMA3 = IsIntel && ((ECX >> 12) & 0x1); ToggleFeature(X86::FeatureFMA3); in AutoDetectSubtargetFeatures()
204 HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); ToggleFeature(X86::FeaturePOPCNT); in AutoDetectSubtargetFeatures()
205 HasAES = IsIntel && ((ECX >> 25) & 0x1); ToggleFeature(X86::FeatureAES); in AutoDetectSubtargetFeatures()
[all …]
DX86CallingConv.td79 // For integers, ECX can be used as an extra return register
82 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
147 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
200 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
296 // The 'nest' parameter, if any, is passed in ECX.
297 CCIfNest<CCAssignToReg<[ECX]>>,
301 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
314 // The first 2 integer arguments are passed in ECX/EDX
315 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
328 // The first integer argument is passed in ECX
[all …]
DX86SelectionDAGInfo.cpp131 X86::ECX, in EmitTargetCodeForMemset()
150 X86::ECX, in EmitTargetCodeForMemset()
221 X86::ECX, in EmitTargetCodeForMemcpy()
DX86RegisterInfo.cpp83 case X86::ECX: case X86::R12: return 2; in getCompactUnwindRegNum()
650 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
662 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
699 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
735 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
736 return X86::ECX; in getX86SubSuperRegister()
771 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegister()
DX86RegisterInfo.td102 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>;
126 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
304 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
342 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)> {
353 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)> {
381 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)> {
DX86InstrControl.td84 let Uses = [ECX] in
91 let Uses = [ECX] in
141 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
180 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
DX86InstrCompiler.td244 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
259 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
262 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
265 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
282 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
310 let Defs = [EAX, ECX, EFLAGS],
490 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
491 Uses = [EAX, EBX, ECX, EDX],
667 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
DX86InstrInfo.td701 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
706 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1169 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1189 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1190 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
/external/llvm/test/CodeGen/X86/
Dabi-isel.ll70 ; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e..]]
71 ; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]])
78 ; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L0$pb([[EAX]]), [[ECX:%e..]]
79 ; DARWIN-32-PIC-NEXT: movl ([[ECX]]), [[ECX:%e..]]
81 ; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]])
142 ; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[ECX:%e.x]]
143 ; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]])
150 ; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L1$pb([[EAX]]), [[ECX:%e.x]]
151 ; DARWIN-32-PIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]]
153 ; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]])
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Dfast-cc-pass-in-regs.ll14 ; CHECK: mov{{.*}}EAX, ECX
21 ; CHECK: mov{{.*}}ECX, 3
27 ; CHECK: mov{{.*}}EAX, ECX
D2010-04-08-CoalescerBug.ll6 ; REP_MOVSD %ECX<imp-def,dead>, %EDI<imp-def,dead>, %ESI<imp-def,dead>, %ECX<imp-use,kill>, %EDI<im…
Dloop-strength-reduce4.ll7 ; STATIC: movl $-64, [[ECX:%e..]]
9 ; STATIC: movl [[EAX:%e..]], _state+76([[ECX]])
10 ; STATIC: addl $16, [[ECX]]
/external/qemu/distrib/sdl-1.2.12/src/hermes/
DHeadMMX.h81 #pragma aux ConvertMMX "_*" modify [EAX EBX ECX EDX ESI EDI]
83 #pragma aux ClearMMX_32 "_*" modify [EAX EBX ECX EDX ESI EDI]
84 #pragma aux ClearMMX_24 "_*" modify [EAX EBX ECX EDX ESI EDI]
85 #pragma aux ClearMMX_16 "_*" modify [EAX EBX ECX EDX ESI EDI]
86 #pragma aux ClearMMX_8 "_*" modify [EAX EBX ECX EDX ESI EDI]
DHeadX86.h138 #pragma aux ConvertX86 "_*" modify [EAX EBX ECX EDX ESI EDI]
139 #pragma aux ClearX86_32 "_*" modify [EAX EBX ECX EDX ESI EDI]
140 #pragma aux ClearX86_24 "_*" modify [EAX EBX ECX EDX ESI EDI]
141 #pragma aux ClearX86_16 "_*" modify [EAX EBX ECX EDX ESI EDI]
142 #pragma aux ClearX86_8 "_*" modify [EAX EBX ECX EDX ESI EDI]
/external/llvm/lib/Support/
DHost.cpp109 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUName() local
110 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) in getHostCPUName()
116 bool HasSSE3 = (ECX & 0x1); in getHostCPUName()
117 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getHostCPUName()
/external/qemu/target-i386/
Dexec.h38 #define ECX (env->regs[R_ECX]) macro
291 ECX = env->regs[R_ECX]; in env_to_regs()
319 env->regs[R_ECX] = ECX; in regs_to_env()
Dop_helper.c382 stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX); in switch_tss()
396 stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX); in switch_tss()
448 ECX = new_regs[1]; in switch_tss()
1019 ECX = env->eip + next_eip_addend; in helper_syscall()
1042 ECX = (uint32_t)(env->eip + next_eip_addend); in helper_syscall()
1083 env->eip = ECX; in helper_sysret()
1090 env->eip = (uint32_t)ECX; in helper_sysret()
1106 env->eip = (uint32_t)ECX; in helper_sysret()
1426 stq_phys(sm_state + 0x7ff0, ECX); in do_smm_enter()
1457 stl_phys(sm_state + 0x7fd4, ECX); in do_smm_enter()
[all …]
/external/llvm/include/llvm/Support/
DSolaris.h27 #undef ECX
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h7 #define ECX 1 macro
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.h39 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
DX86MCTargetDesc.cpp130 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; in getX86RegNum()
145 return N86::ECX; in getX86RegNum()
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h126 ENTRY(ECX) \
144 ENTRY(ECX) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c84 GENOFFSET(X86,x86,ECX); in foo()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-x86-linux.c379 SC2(ecx,ECX); in synth_ucontext()
/external/qemu-pc-bios/bochs/
Dbochs.h55 #undef ECX

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