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Searched refs:FSQRT (Results 1 – 25 of 28) sorted by relevance

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/external/valgrind/main/none/tests/ppc64/
Dround.c33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
902 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1010 case FSQRT: in check_double_guarded_arithmetic_op()
1115 case FSQRT: in check_double_guarded_arithmetic_op()
1184 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
/external/valgrind/main/none/tests/ppc32/
Dround.c33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator
902 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) in check_double_guarded_arithmetic_op()
1010 case FSQRT: in check_double_guarded_arithmetic_op()
1115 case FSQRT: in check_double_guarded_arithmetic_op()
1184 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrFPU.td110 def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIC_FPUs>;
135 def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>;
DMBlazeInstrFormats.td27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp170 case ISD::FSQRT: in LegalizeOp()
DLegalizeFloatTypes.cpp89 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
863 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
DLegalizeVectorTypes.cpp87 case ISD::FSQRT: in ScalarizeVectorResult()
464 case ISD::FSQRT: in SplitVectorResult()
1291 case ISD::FSQRT: in WidenVectorResult()
DSelectionDAGBuilder.cpp4626 setValue(&I, DAG.getNode(ISD::FSQRT, dl, in visitIntrinsicCall()
5347 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), in visitCall()
/external/oprofile/events/ppc64/ibm-compat-v1/
Devents28 …FPU_FLOP_GRP2 : (Group 2 pm_compat_utilization2) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
/external/oprofile/events/ppc64/970MP/
Devents68 …rs:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
133 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
134 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
228 …:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
468 …zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
/external/oprofile/events/ppc64/970/
Devents63 …rs:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
128 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
129 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
223 …:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
463 …zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
/external/llvm/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp235 case 0x380: return MBlaze::FSQRT; in decodeFADD()
/external/llvm/lib/Target/Alpha/
DAlphaISelLowering.cpp119 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in AlphaTargetLowering()
120 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in AlphaTargetLowering()
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td131 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
/external/oprofile/events/ppc64/power6/
Devents742 …0 name:PM_FPU0_FSQRT_FDIV_GRP120 : (Group 120 pm_fpu0_flop) FPU0 executed FSQRT or FDIV instruction
746 …:PM_FPU0_FLOP_GRP121 : (Group 121 pm_fpu0_misc) FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
766 …0 name:PM_FPU1_FSQRT_FDIV_GRP124 : (Group 124 pm_fpu1_flop) FPU1 executed FSQRT or FDIV instruction
770 …:PM_FPU1_FLOP_GRP125 : (Group 125 pm_fpu1_misc) FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
790 …1000 name:PM_FPU_FSQRT_FDIV_GRP128 : (Group 128 pm_fpu_flop) FPU executed FSQRT or FDIV instruction
791 …ame:PM_FPU_FLOP_GRP128 : (Group 128 pm_fpu_flop) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
1144 …mum:1000 name:PM_FPU_FSQRT_FDIV_GRP187 : (Group 187 pm_hpm1) FPU executed FSQRT or FDIV instruction
/external/oprofile/events/ppc64/power4/
Devents163 …:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP15 : (Group 15 pm_fpu1) FPU executed FSQRT instruction
308 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP30 : (Group 30 pm_fpu4) FPU0 executed FSQRT instruction
309 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP30 : (Group 30 pm_fpu4) FPU1 executed FSQRT instruction
553 …:zero minimum:1000 name:PM_FPU_FSQRT_GRP54 : (Group 54 pm_pe_bench1) FPU executed FSQRT instruction
/external/oprofile/events/ppc64/power5++/
Devents519 …:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP83 : (Group 83 pm_fpu2) FPU executed FSQRT instruction
536 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU0 executed FSQRT instruction
537 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU1 executed FSQRT instruction
891 …um:zero minimum:1000 name:PM_FPU_FSQRT_GRP145 : (Group 145 pm_fpuX6) FPU executed FSQRT instruction
928 … um:zero minimum:1000 name:PM_FPU_FSQRT_GRP151 : (Group 151 pm_flop) FPU executed FSQRT instruction
/external/oprofile/events/ppc64/power5+/
Devents678 …:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP83 : (Group 83 pm_fpu2) FPU executed FSQRT instruction
701 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU0 executed FSQRT instruction
702 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU1 executed FSQRT instruction
1174 …um:zero minimum:1000 name:PM_FPU_FSQRT_GRP145 : (Group 145 pm_fpuX6) FPU executed FSQRT instruction
1223 … um:zero minimum:1000 name:PM_FPU_FSQRT_GRP151 : (Group 151 pm_flop) FPU executed FSQRT instruction
/external/oprofile/events/ppc64/power5/
Devents654 …:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP80 : (Group 80 pm_fpu2) FPU executed FSQRT instruction
677 … um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP83 : (Group 83 pm_fpu5) FPU0 executed FSQRT instruction
678 … um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP83 : (Group 83 pm_fpu5) FPU1 executed FSQRT instruction
1134 …um:zero minimum:1000 name:PM_FPU_FSQRT_GRP140 : (Group 140 pm_fpuX6) FPU executed FSQRT instruction
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp220 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in SPUTargetLowering()
221 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in SPUTargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td360 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp726 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
812 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in X86TargetLowering()
846 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in X86TargetLowering()
998 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); in X86TargetLowering()
1005 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in X86TargetLowering()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp139 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
140 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
DPPCInstrInfo.td995 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),

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