1//===- MBlazeInstrFPU.td - MBlaze FPU Instruction defs -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// MBlaze profiles and nodes 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// MBlaze Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18//===----------------------------------------------------------------------===// 19// Memory Access Instructions 20//===----------------------------------------------------------------------===// 21class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> : 22 TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr), 23 !strconcat(instr_asm, " $dst, $addr"), 24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>; 25 26class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> : 27 TB<op, (outs GPR:$dst), (ins memri:$addr), 28 !strconcat(instr_asm, " $dst, $addr"), 29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>; 30 31class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> : 32 TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr), 33 !strconcat(instr_asm, " $dst, $addr"), 34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>; 35 36class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> : 37 TB<op, (outs), (ins GPR:$dst, memrr:$addr), 38 !strconcat(instr_asm, " $dst, $addr"), 39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>; 40 41class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode, 42 InstrItinClass itin> : 43 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 44 !strconcat(instr_asm, " $dst, $b, $c"), 45 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>; 46 47class CmpFN<bits<6> op, bits<11> flags, string instr_asm, 48 InstrItinClass itin> : 49 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 50 !strconcat(instr_asm, " $dst, $b, $c"), 51 [], itin>; 52 53class ArithFR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode, 54 InstrItinClass itin> : 55 TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 56 !strconcat(instr_asm, " $dst, $c, $b"), 57 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>; 58 59class LogicFI<bits<6> op, string instr_asm> : 60 TB<op, (outs GPR:$dst), (ins GPR:$b, fimm:$c), 61 !strconcat(instr_asm, " $dst, $b, $c"), 62 [], IIC_ALU>; 63 64let rb=0 in { 65 class ArithF2<bits<6> op, bits<11> flags, string instr_asm, 66 InstrItinClass itin> : 67 TA<op, flags, (outs GPR:$dst), (ins GPR:$b), 68 !strconcat(instr_asm, " $dst, $b"), 69 [], itin>; 70 71 class ArithIF<bits<6> op, bits<11> flags, string instr_asm, 72 InstrItinClass itin> : 73 TA<op, flags, (outs GPR:$dst), (ins GPR:$b), 74 !strconcat(instr_asm, " $dst, $b"), 75 [], itin>; 76 77 class ArithFI<bits<6> op, bits<11> flags, string instr_asm, 78 InstrItinClass itin> : 79 TA<op, flags, (outs GPR:$dst), (ins GPR:$b), 80 !strconcat(instr_asm, " $dst, $b"), 81 [], itin>; 82} 83 84//===----------------------------------------------------------------------===// 85// Pseudo instructions 86//===----------------------------------------------------------------------===// 87 88//===----------------------------------------------------------------------===// 89// FPU Arithmetic Instructions 90//===----------------------------------------------------------------------===// 91let Predicates=[HasFPU] in { 92 def FORI : LogicFI<0x28, "ori ">; 93 def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIC_FPU>; 94 def FRSUB : ArithFR<0x16, 0x080, "frsub ", fsub, IIC_FPU>; 95 def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIC_FPU>; 96 def FDIV : ArithF<0x16, 0x180, "fdiv ", fdiv, IIC_FPUd>; 97} 98 99let Predicates=[HasFPU], isCodeGenOnly=1 in { 100 def LWF : LoadFM<0x32, "lw ", load>; 101 def LWFI : LoadFMI<0x3A, "lwi ", load>; 102 103 def SWF : StoreFM<0x36, "sw ", store>; 104 def SWFI : StoreFMI<0x3E, "swi ", store>; 105} 106 107let Predicates=[HasFPU,HasSqrt] in { 108 def FLT : ArithIF<0x16, 0x280, "flt ", IIC_FPUf>; 109 def FINT : ArithFI<0x16, 0x300, "fint ", IIC_FPUi>; 110 def FSQRT : ArithF2<0x16, 0x380, "fsqrt ", IIC_FPUs>; 111} 112 113let isAsCheapAsAMove = 1 in { 114 def FCMP_UN : CmpFN<0x16, 0x200, "fcmp.un", IIC_FPUc>; 115 def FCMP_LT : CmpFN<0x16, 0x210, "fcmp.lt", IIC_FPUc>; 116 def FCMP_EQ : CmpFN<0x16, 0x220, "fcmp.eq", IIC_FPUc>; 117 def FCMP_LE : CmpFN<0x16, 0x230, "fcmp.le", IIC_FPUc>; 118 def FCMP_GT : CmpFN<0x16, 0x240, "fcmp.gt", IIC_FPUc>; 119 def FCMP_NE : CmpFN<0x16, 0x250, "fcmp.ne", IIC_FPUc>; 120 def FCMP_GE : CmpFN<0x16, 0x260, "fcmp.ge", IIC_FPUc>; 121} 122 123 124let usesCustomInserter = 1 in { 125 def Select_FCC : MBlazePseudo<(outs GPR:$dst), 126 (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), 127 "; SELECT_FCC PSEUDO!", 128 []>; 129} 130 131// Floating point conversions 132let Predicates=[HasFPU] in { 133 def : Pat<(sint_to_fp GPR:$V), (FLT GPR:$V)>; 134 def : Pat<(fp_to_sint GPR:$V), (FINT GPR:$V)>; 135 def : Pat<(fsqrt GPR:$V), (FSQRT GPR:$V)>; 136} 137 138// SET_CC operations 139let Predicates=[HasFPU] in { 140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ), 141 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 142 (FCMP_EQ GPR:$L, GPR:$R), 2)>; 143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE), 144 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 145 (FCMP_EQ GPR:$L, GPR:$R), 1)>; 146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ), 147 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 148 (FCMP_EQ GPR:$L, GPR:$R), 2)>; 149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE), 150 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 151 (XOR (FCMP_UN GPR:$L, GPR:$R), 152 (FCMP_EQ GPR:$L, GPR:$R)), 2)>; 153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE), 154 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 155 (OR (FCMP_UN GPR:$L, GPR:$R), 156 (FCMP_EQ GPR:$L, GPR:$R)), 2)>; 157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT), 158 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 159 (FCMP_GT GPR:$L, GPR:$R), 2)>; 160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT), 161 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 162 (FCMP_LT GPR:$L, GPR:$R), 2)>; 163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE), 164 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 165 (FCMP_GE GPR:$L, GPR:$R), 2)>; 166 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE), 167 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 168 (FCMP_LE GPR:$L, GPR:$R), 2)>; 169 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT), 170 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 171 (FCMP_GT GPR:$L, GPR:$R), 2)>; 172 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLT), 173 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 174 (FCMP_LT GPR:$L, GPR:$R), 2)>; 175 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE), 176 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 177 (FCMP_GE GPR:$L, GPR:$R), 2)>; 178 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE), 179 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 180 (FCMP_LE GPR:$L, GPR:$R), 2)>; 181 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUEQ), 182 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 183 (OR (FCMP_UN GPR:$L, GPR:$R), 184 (FCMP_EQ GPR:$L, GPR:$R)), 2)>; 185 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUNE), 186 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 187 (FCMP_NE GPR:$L, GPR:$R), 2)>; 188 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT), 189 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 190 (OR (FCMP_UN GPR:$L, GPR:$R), 191 (FCMP_GT GPR:$L, GPR:$R)), 2)>; 192 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT), 193 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 194 (OR (FCMP_UN GPR:$L, GPR:$R), 195 (FCMP_LT GPR:$L, GPR:$R)), 2)>; 196 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE), 197 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 198 (OR (FCMP_UN GPR:$L, GPR:$R), 199 (FCMP_GE GPR:$L, GPR:$R)), 2)>; 200 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE), 201 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 202 (OR (FCMP_UN GPR:$L, GPR:$R), 203 (FCMP_LE GPR:$L, GPR:$R)), 2)>; 204 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO), 205 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 206 (FCMP_UN GPR:$L, GPR:$R), 1)>; 207 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUO), 208 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 209 (FCMP_UN GPR:$L, GPR:$R), 2)>; 210} 211 212// SELECT operations 213def : Pat<(select (i32 GPR:$C), (f32 GPR:$T), (f32 GPR:$F)), 214 (Select_FCC GPR:$T, GPR:$F, GPR:$C, 2)>; 215 216//===----------------------------------------------------------------------===// 217// Patterns for Floating Point Instructions 218//===----------------------------------------------------------------------===// 219def : Pat<(f32 fpimm:$imm), (FORI (i32 R0), fpimm:$imm)>; 220