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Searched refs:IMPLICIT_DEF (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/include/llvm/Target/
DTargetOpcodes.h52 IMPLICIT_DEF = 8, enumerator
DTargetInstrInfo.h66 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
/external/llvm/test/CodeGen/X86/
Dinsertelement-copytoregs.ll1 ; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF
D2008-01-16-InvalidDAGCombineXform.ll1 ; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
/external/llvm/test/CodeGen/PowerPC/
D2006-10-13-Miscompile.ll1 ; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
/external/llvm/lib/CodeGen/
DProcessImplicitDefs.cpp147 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in runOnMachineFunction()
243 RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in runOnMachineFunction()
DMachineSSAUpdater.cpp149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
303 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
DPHIElimination.cpp212 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); in LowerAtomicPHINode()
DTwoAddressInstructionPass.cpp1513 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in EliminateRegSequences()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp184 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
242 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
252 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
667 if (Opc == TargetOpcode::IMPLICIT_DEF) in EmitMachineNode()
DScheduleDAGSDNodes.cpp74 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) in NewSUnit()
498 if (POpc == TargetOpcode::IMPLICIT_DEF) { in InitNodeNumDefs()
DScheduleDAGRRList.cpp2007 Opc == TargetOpcode::IMPLICIT_DEF) in UnscheduledNode()
2030 if (POpc == TargetOpcode::IMPLICIT_DEF) in UnscheduledNode()
DFastISel.cpp204 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); in materializeRegForValue()
/external/llvm/lib/Target/Mips/
DMipsISelDAGToDAG.cpp234 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectLoadFp64()
421 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0); in Select()
/external/llvm/lib/Target/PowerPC/
DPPCCodeEmitter.cpp124 case TargetOpcode::IMPLICIT_DEF: in emitBasicBlock()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp308 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h276 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp634 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in Select()
712 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in Select()
DSystemZInstrInfo.td1092 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1130 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1136 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1141 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4415 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4417 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4419 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4422 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4424 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4426 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4429 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4430 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4433 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4434 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
[all …]
DARMISelDAGToDAG.cpp1533 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); in SelectVLD()
1643 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) in SelectVST()
1683 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVST()
1801 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVLDSTLane()
1931 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVTBL()
/external/llvm/lib/Target/Blackfin/
DBlackfinInstrInfo.td478 (STORE8p (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
517 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
529 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
/external/llvm/lib/Target/X86/
DX86InstrSSE.td177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
517 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
519 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
521 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
523 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
526 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
528 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
[all …]
DX86CodeEmitter.cpp740 case TargetOpcode::IMPLICIT_DEF: in emitInstruction()
DX86ISelDAGToDAG.cpp1472 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadAdd()
1634 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadArith()

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