| /external/llvm/include/llvm/CodeGen/ |
| D | LiveInterval.h | 172 bool operator<(const LiveRange &LR) const {
173 return start < LR.start || (start == LR.start && end < LR.end);
175 bool operator==(const LiveRange &LR) const {
176 return start == LR.start && end == LR.end;
188 raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);
191 inline bool operator<(SlotIndex V, const LiveRange &LR) {
192 return V < LR.start;
195 inline bool operator<(const LiveRange &LR, SlotIndex V) {
196 return LR.start < V;
321 bool isOnlyLROfValNo(const LiveRange *LR) {
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| /external/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 212 void RAFast::addKillFlag(const LiveReg &LR) { in addKillFlag() argument
213 if (!LR.LastUse) return; in addKillFlag()
214 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); in addKillFlag()
215 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
216 if (MO.getReg() == LR.PhysReg) in addKillFlag()
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
226 const LiveReg &LR = LRI->second; in killVirtReg() local
227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); in killVirtReg()
228 PhysRegState[LR.PhysReg] = regFree; in killVirtReg()
256 LiveReg &LR = LRI->second; in spillVirtReg() local
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| D | LiveInterval.cpp | 249 LiveInterval::addRangeFrom(LiveRange LR, iterator From) { in addRangeFrom() argument
250 SlotIndex Start = LR.start, End = LR.end; in addRangeFrom()
257 if (LR.valno == B->valno) { in addRangeFrom()
274 if (LR.valno == it->valno) { in addRangeFrom()
294 return ranges.insert(it, LR); in addRangeFrom()
531 iterator LR = I++; in MergeValueNumberInto() local
532 if (LR->valno != V1) continue; // Not a V1 LiveRange. in MergeValueNumberInto()
536 if (LR != begin()) { in MergeValueNumberInto()
537 iterator Prev = LR-1; in MergeValueNumberInto()
538 if (Prev->valno == V2 && Prev->end == LR->start) { in MergeValueNumberInto()
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| D | LiveIntervalAnalysis.cpp | 335 LiveRange LR(defIndex, killIdx, ValNo); in handleVirtualRegisterDef() local
336 interval.addRange(LR); in handleVirtualRegisterDef()
337 DEBUG(dbgs() << " +" << LR << "\n"); in handleVirtualRegisterDef()
365 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo); in handleVirtualRegisterDef() local
366 interval.addRange(LR); in handleVirtualRegisterDef()
367 DEBUG(dbgs() << " +" << LR); in handleVirtualRegisterDef()
386 LiveRange LR(Start, killIdx, ValNo); in handleVirtualRegisterDef() local
387 interval.addRange(LR); in handleVirtualRegisterDef()
388 DEBUG(dbgs() << " +" << LR); in handleVirtualRegisterDef()
440 LiveRange LR(DefIndex, RedefIndex, ValNo); in handleVirtualRegisterDef() local
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| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | PointerArithChecker.cpp | 43 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
45 if (!LR || !RV.isConstant()) in checkPreStmt()
50 if (isa<VarRegion>(LR) || isa<CodeTextRegion>(LR) || in checkPreStmt()
51 isa<CompoundLiteralRegion>(LR)) { in checkPreStmt()
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| D | PointerSubChecker.cpp | 46 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
49 if (!(LR && RR)) in checkPreStmt()
52 const MemRegion *BaseLR = LR->getBaseRegion(); in checkPreStmt()
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| /external/clang/test/PCH/ |
| D | cxx-reference.h | 3 typedef char (&LR);
10 LR &lrlr = c;
11 LR &&rrlr = c;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 129 MBB.addLiveIn(XCore::LR); in emitPrologue()
150 MachineLocation CSSrc(XCore::LR); in emitPrologue()
156 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
157 MBB.addLiveIn(XCore::LR); in emitPrologue()
163 MachineLocation CSSrc(XCore::LR); in emitPrologue()
256 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII); in emitEpilogue()
343 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR); in processFunctionBeforeCalleeSavedScan()
347 MF.getRegInfo().setPhysRegUnused(XCore::LR); in processFunctionBeforeCalleeSavedScan()
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| D | XCoreRegisterInfo.td | 41 def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
54 def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
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| D | XCoreRegisterInfo.cpp | 41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) { in XCoreRegisterInfo()
80 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
93 Reserved.set(XCore::LR); in getReservedRegs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), in ARMBaseRegisterInfo()
67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
78 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
410 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
415 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, in getRawAllocationOrder()
422 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, in getRawAllocationOrder()
427 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, in getRawAllocationOrder()
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
439 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
446 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, in getRawAllocationOrder()
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| D | ARMFrameLowering.cpp | 161 case ARM::LR: in emitPrologue()
560 if (Reg == ARM::LR) { in emitPushInst()
629 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) { in emitPopInst()
661 Regs[0] = ARM::LR; in emitPopInst()
877 MF.getRegInfo().setPhysRegUsed(ARM::LR); in processFunctionBeforeCalleeSavedScan()
921 if (Reg == ARM::LR) in processFunctionBeforeCalleeSavedScan()
929 case ARM::LR: in processFunctionBeforeCalleeSavedScan()
948 case ARM::LR: in processFunctionBeforeCalleeSavedScan()
998 MF.getRegInfo().setPhysRegUsed(ARM::LR); in processFunctionBeforeCalleeSavedScan()
1001 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); in processFunctionBeforeCalleeSavedScan()
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| D | Thumb1FrameLowering.cpp | 92 case ARM::LR: in emitPrologue()
306 if (Reg == ARM::LR) { in spillCalleeSavedRegisters()
342 if (Reg == ARM::LR) { in restoreCalleeSavedRegisters()
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| D | ARMRegisterInfo.td | 69 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
206 SP, LR, PC)> {
207 // Allocate LR as the first CSR since it is always saved anyway.
212 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
223 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
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| /external/llvm/include/llvm/ADT/ |
| D | ImmutableSet.h | 498 TreeTy *LR = getRight(L); in balanceTree() local
500 if (getHeight(LL) >= getHeight(LR)) in balanceTree()
501 return createNode(LL, L, createNode(LR,V,R)); in balanceTree()
503 assert(!isEmpty(LR) && "LR cannot be empty because it has a height >= 1"); in balanceTree()
505 TreeTy *LRL = getLeft(LR); in balanceTree()
506 TreeTy *LRR = getRight(LR); in balanceTree()
508 return createNode(createNode(LL,L,LRL), LR, createNode(LRR,V,R)); in balanceTree()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUFrameLowering.h | 27 std::pair<unsigned, int> LR[1]; variable
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| D | SPUTargetMachine.cpp | 31 return &LR[0]; in getCalleeSaveSpillSlots()
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| D | SPUFrameLowering.cpp | 37 LR[0].first = SPU::R0; in SPUFrameLowering()
38 LR[0].second = 16; in SPUFrameLowering()
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| /external/icu4c/data/region/ |
| D | ps.txt | 52 LR{"لایبریا"}
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| D | sl.txt | 146 HK{"Posebno administrativno območje LR Kitajske Hong Kong"}
183 LR{"Liberija"}
200 MO{"Posebno administrativno območje LR Kitajske Macao"}
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| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| D | XCoreMCTargetDesc.cpp | 44 InitXCoreMCRegisterInfo(X, XCore::LR); in createXCoreMCRegisterInfo()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 449 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); in emitPrologue()
489 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; in emitPrologue()
723 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { in MustSaveLR() argument
730 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); in MustSaveLR()
741 unsigned LR = RegInfo->getRARegister(); in processFunctionBeforeCalleeSavedScan() local
742 FI->setMustSaveLR(MustSaveLR(MF, LR)); in processFunctionBeforeCalleeSavedScan()
743 MF.getRegInfo().setPhysRegUnused(LR); in processFunctionBeforeCalleeSavedScan()
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| /external/llvm/test/CodeGen/Generic/ |
| D | badCallArgLRLLVM.ll | 9 ; ERROR: In call instr, no LR for arg: 0x1009e0740
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| /external/dropbear/libtommath/tombc/ |
| D | grammar.txt | 16 // LR(1) !!!?
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCTargetDesc.cpp | 48 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; in createPPCMCRegisterInfo()
|