| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) in emitPrologue()
592 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) in emitEpilogue()
670 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; in emitEpilogue()
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| D | PPCRegisterInfo.cpp | 336 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; in eliminateCallFramePseudoInstr()
648 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) in eliminateFrameIndex()
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| D | PPCInstrInfo.td | 900 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1348 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1350 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1361 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
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| D | PPCISelLowering.cpp | 4786 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); in EmitPartwordAtomicBinary()
5120 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeAsmBackend.cpp | 76 case MBlaze::ORI: return MBlaze::ORI32; in getRelaxedOpcode()
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| D | MBlazeInstrInfo.td | 417 def ORI : LogicI<0x28, "ori ", or>;
727 def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>;
852 def : Pat<(MBWrapper tglobaladdr:$in), (ORI (i32 R0), tglobaladdr:$in)>;
853 def : Pat<(MBWrapper tjumptable:$in), (ORI (i32 R0), tjumptable:$in)>;
854 def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>;
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| D | MBlazeInstrFormats.td | 19 def FRRI : Format<2>; // ADDI, ORI, etc.
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| /external/v8/src/mips/ |
| D | assembler-mips.cc | 1184 GenInstrImmediate(ORI, rs, rt, j); in ori()
2021 ASSERT(((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) || in target_address_at()
2023 (instr2 & kOpcodeMask) == ORI || in target_address_at()
2029 } else if ((instr2 & kOpcodeMask) == ORI) { in target_address_at()
2034 } else if ((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) { in target_address_at()
2055 CHECK(((instr1 & kOpcodeMask) == LUI && (instr2 & kOpcodeMask) == ORI) || in set_target_address_at()
2057 (instr2 & kOpcodeMask)== ORI || in set_target_address_at()
2074 *(p+1) = ORI | rt_code | (itarget & kImm16Mask); in set_target_address_at()
2084 *(p+1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask); in set_target_address_at()
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| D | constants-mips.cc | 315 case ORI: in InstructionType()
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| D | assembler-mips-inl.h | 238 (instr1 & kOpcodeMask) == ORI && in IsPatchedReturnSequence()
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| D | constants-mips.h | 214 ORI = ((1 << 3) + 5) << kOpcodeShift, enumerator
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| D | disasm-mips.cc | 832 case ORI: in DecodeTypeImmediate()
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| D | simulator-mips.cc | 2032 case ORI: in DecodeTypeImmediate()
2154 case ORI: in DecodeTypeImmediate()
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| /external/qemu/tcg/ppc64/ |
| D | tcg-target.c | 305 #define ORI OPCD( 24) macro
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); in tcg_out_movi32()
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16); in tcg_out_movi()
1335 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0]) in tcg_out_op()
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| /external/qemu/tcg/ppc/ |
| D | tcg-target.c | 317 #define ORI OPCD(24) macro
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); in tcg_out_movi()
1448 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0]) in tcg_out_op()
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| /external/llvm/test/CodeGen/CellSPU/ |
| D | or_ops.ll | 182 ; ORI instruction generation (i32 data type):
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
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| /external/icu4c/common/ |
| D | ucnvisci.c | 94 ORI = 0x47, enumerator
147 { ORIYA, ORI_MASK, ORI },
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUInstrInfo.td | 1607 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1615 defm ORI : BitwiseOrImm;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2297 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) in visitAND() local
2298 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) in visitAND()
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| /external/srec/config/en.us/dictionary/ |
| D | c0.6 | 82207 ORI AO1 R IY0
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