1//===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Instruction format superclass 12//===----------------------------------------------------------------------===// 13include "MBlazeInstrFormats.td" 14 15//===----------------------------------------------------------------------===// 16// MBlaze type profiles 17//===----------------------------------------------------------------------===// 18 19// def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>; 20def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 21def SDT_MBlazeIRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 22def SDT_MBlazeJmpLink : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 23def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 24def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 25 26//===----------------------------------------------------------------------===// 27// MBlaze specific nodes 28//===----------------------------------------------------------------------===// 29 30def MBlazeRet : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet, 31 [SDNPHasChain, SDNPOptInGlue]>; 32def MBlazeIRet : SDNode<"MBlazeISD::IRet", SDT_MBlazeIRet, 33 [SDNPHasChain, SDNPOptInGlue]>; 34 35def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink, 36 [SDNPHasChain,SDNPOptInGlue,SDNPOutGlue, 37 SDNPVariadic]>; 38 39def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>; 40 41def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MBCallSeqStart, 42 [SDNPHasChain, SDNPOutGlue]>; 43 44def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd, 45 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 46 47//===----------------------------------------------------------------------===// 48// MBlaze Instruction Predicate Definitions. 49//===----------------------------------------------------------------------===// 50// def HasPipe3 : Predicate<"Subtarget.hasPipe3()">; 51def HasBarrel : Predicate<"Subtarget.hasBarrel()">; 52// def NoBarrel : Predicate<"!Subtarget.hasBarrel()">; 53def HasDiv : Predicate<"Subtarget.hasDiv()">; 54def HasMul : Predicate<"Subtarget.hasMul()">; 55// def HasFSL : Predicate<"Subtarget.hasFSL()">; 56// def HasEFSL : Predicate<"Subtarget.hasEFSL()">; 57// def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">; 58// def HasException : Predicate<"Subtarget.hasException()">; 59def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">; 60def HasFPU : Predicate<"Subtarget.hasFPU()">; 61// def HasESR : Predicate<"Subtarget.hasESR()">; 62// def HasPVR : Predicate<"Subtarget.hasPVR()">; 63def HasMul64 : Predicate<"Subtarget.hasMul64()">; 64def HasSqrt : Predicate<"Subtarget.hasSqrt()">; 65// def HasMMU : Predicate<"Subtarget.hasMMU()">; 66 67//===----------------------------------------------------------------------===// 68// MBlaze Operand, Complex Patterns and Transformations Definitions. 69//===----------------------------------------------------------------------===// 70 71def MBlazeMemAsmOperand : AsmOperandClass { 72 let Name = "Mem"; 73 let SuperClasses = []; 74} 75 76def MBlazeFslAsmOperand : AsmOperandClass { 77 let Name = "Fsl"; 78 let SuperClasses = []; 79} 80 81// Instruction operand types 82def brtarget : Operand<OtherVT>; 83def calltarget : Operand<i32>; 84def simm16 : Operand<i32>; 85def uimm5 : Operand<i32>; 86def uimm15 : Operand<i32>; 87def fimm : Operand<f32>; 88 89// Unsigned Operand 90def uimm16 : Operand<i32> { 91 let PrintMethod = "printUnsignedImm"; 92} 93 94// FSL Operand 95def fslimm : Operand<i32> { 96 let PrintMethod = "printFSLImm"; 97 let ParserMatchClass = MBlazeFslAsmOperand; 98} 99 100// Address operand 101def memri : Operand<i32> { 102 let PrintMethod = "printMemOperand"; 103 let MIOperandInfo = (ops GPR, simm16); 104 let ParserMatchClass = MBlazeMemAsmOperand; 105} 106 107def memrr : Operand<i32> { 108 let PrintMethod = "printMemOperand"; 109 let MIOperandInfo = (ops GPR, GPR); 110 let ParserMatchClass = MBlazeMemAsmOperand; 111} 112 113// Node immediate fits as 16-bit sign extended on target immediate. 114def immSExt16 : PatLeaf<(imm), [{ 115 return (N->getZExtValue() >> 16) == 0; 116}]>; 117 118// Node immediate fits as 16-bit zero extended on target immediate. 119// The LO16 param means that only the lower 16 bits of the node 120// immediate are caught. 121// e.g. addiu, sltiu 122def immZExt16 : PatLeaf<(imm), [{ 123 return (N->getZExtValue() >> 16) == 0; 124}]>; 125 126// FSL immediate field must fit in 4 bits. 127def immZExt4 : PatLeaf<(imm), [{ 128 return N->getZExtValue() == ((N->getZExtValue()) & 0xf) ; 129}]>; 130 131// shamt field must fit in 5 bits. 132def immZExt5 : PatLeaf<(imm), [{ 133 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ; 134}]>; 135 136// MBlaze Address Mode. SDNode frameindex could possibily be a match 137// since load and store instructions from stack used it. 138def iaddr : ComplexPattern<i32, 2, "SelectAddrRegImm", [frameindex], []>; 139def xaddr : ComplexPattern<i32, 2, "SelectAddrRegReg", [], []>; 140 141//===----------------------------------------------------------------------===// 142// Pseudo instructions 143//===----------------------------------------------------------------------===// 144 145// As stack alignment is always done with addiu, we need a 16-bit immediate 146let Defs = [R1], Uses = [R1] in { 147def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt), 148 "#ADJCALLSTACKDOWN $amt", 149 [(callseq_start timm:$amt)]>; 150def ADJCALLSTACKUP : MBlazePseudo<(outs), 151 (ins uimm16:$amt1, simm16:$amt2), 152 "#ADJCALLSTACKUP $amt1", 153 [(callseq_end timm:$amt1, timm:$amt2)]>; 154} 155 156//===----------------------------------------------------------------------===// 157// Instructions specific format 158//===----------------------------------------------------------------------===// 159 160//===----------------------------------------------------------------------===// 161// Arithmetic Instructions 162//===----------------------------------------------------------------------===// 163class Arith<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode, 164 InstrItinClass itin> : 165 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 166 !strconcat(instr_asm, " $dst, $b, $c"), 167 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>; 168 169class ArithI<bits<6> op, string instr_asm, SDNode OpNode, 170 Operand Od, PatLeaf imm_type> : 171 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c), 172 !strconcat(instr_asm, " $dst, $b, $c"), 173 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_ALU>; 174 175class ArithI32<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> : 176 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c), 177 !strconcat(instr_asm, " $dst, $b, $c"), 178 [], IIC_ALU>; 179 180class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode, 181 Operand Od, PatLeaf imm_type> : 182 SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c), 183 !strconcat(instr_asm, " $dst, $b, $c"), 184 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_SHT>; 185 186class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode, 187 InstrItinClass itin> : 188 TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 189 !strconcat(instr_asm, " $dst, $c, $b"), 190 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>; 191 192class ArithRI<bits<6> op, string instr_asm, SDNode OpNode, 193 Operand Od, PatLeaf imm_type> : 194 TBR<op, (outs GPR:$dst), (ins Od:$b, GPR:$c), 195 !strconcat(instr_asm, " $dst, $c, $b"), 196 [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIC_ALU>; 197 198class ArithN<bits<6> op, bits<11> flags, string instr_asm, 199 InstrItinClass itin> : 200 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 201 !strconcat(instr_asm, " $dst, $b, $c"), 202 [], itin>; 203 204class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> : 205 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c), 206 !strconcat(instr_asm, " $dst, $b, $c"), 207 [], IIC_ALU>; 208 209class ArithRN<bits<6> op, bits<11> flags, string instr_asm, 210 InstrItinClass itin> : 211 TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b), 212 !strconcat(instr_asm, " $dst, $b, $c"), 213 [], itin>; 214 215class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> : 216 TBR<op, (outs GPR:$dst), (ins Od:$c, GPR:$b), 217 !strconcat(instr_asm, " $dst, $b, $c"), 218 [], IIC_ALU>; 219 220//===----------------------------------------------------------------------===// 221// Misc Arithmetic Instructions 222//===----------------------------------------------------------------------===// 223 224class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> : 225 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 226 !strconcat(instr_asm, " $dst, $b, $c"), 227 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], IIC_ALU>; 228 229class LogicI<bits<6> op, string instr_asm, SDNode OpNode> : 230 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c), 231 !strconcat(instr_asm, " $dst, $b, $c"), 232 [(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))], 233 IIC_ALU>; 234 235class LogicI32<bits<6> op, string instr_asm> : 236 TB<op, (outs GPR:$dst), (ins GPR:$b, uimm16:$c), 237 !strconcat(instr_asm, " $dst, $b, $c"), 238 [], IIC_ALU>; 239 240class PatCmp<bits<6> op, bits<11> flags, string instr_asm> : 241 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c), 242 !strconcat(instr_asm, " $dst, $b, $c"), 243 [], IIC_ALU>; 244 245//===----------------------------------------------------------------------===// 246// Memory Access Instructions 247//===----------------------------------------------------------------------===// 248 249let mayLoad = 1 in { 250class LoadM<bits<6> op, bits<11> flags, string instr_asm> : 251 TA<op, flags, (outs GPR:$dst), (ins memrr:$addr), 252 !strconcat(instr_asm, " $dst, $addr"), 253 [], IIC_MEMl>; 254} 255 256class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> : 257 TB<op, (outs GPR:$dst), (ins memri:$addr), 258 !strconcat(instr_asm, " $dst, $addr"), 259 [(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>; 260 261let mayStore = 1 in { 262class StoreM<bits<6> op, bits<11> flags, string instr_asm> : 263 TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr), 264 !strconcat(instr_asm, " $dst, $addr"), 265 [], IIC_MEMs>; 266} 267 268class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> : 269 TB<op, (outs), (ins GPR:$dst, memri:$addr), 270 !strconcat(instr_asm, " $dst, $addr"), 271 [(OpNode (i32 GPR:$dst), iaddr:$addr)], IIC_MEMs>; 272 273//===----------------------------------------------------------------------===// 274// Branch Instructions 275//===----------------------------------------------------------------------===// 276class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : 277 TA<op, flags, (outs), (ins GPR:$target), 278 !strconcat(instr_asm, " $target"), 279 [], IIC_BR> { 280 let rd = 0x0; 281 let ra = br; 282 let Form = FCCR; 283} 284 285class BranchI<bits<6> op, bits<5> br, string instr_asm> : 286 TB<op, (outs), (ins brtarget:$target), 287 !strconcat(instr_asm, " $target"), 288 [], IIC_BR> { 289 let rd = 0; 290 let ra = br; 291 let Form = FCCI; 292} 293 294//===----------------------------------------------------------------------===// 295// Branch and Link Instructions 296//===----------------------------------------------------------------------===// 297class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : 298 TA<op, flags, (outs), (ins GPR:$link, GPR:$target, variable_ops), 299 !strconcat(instr_asm, " $link, $target"), 300 [], IIC_BRl> { 301 let ra = br; 302 let Form = FRCR; 303} 304 305class BranchLI<bits<6> op, bits<5> br, string instr_asm> : 306 TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops), 307 !strconcat(instr_asm, " $link, $target"), 308 [], IIC_BRl> { 309 let ra = br; 310 let Form = FRCI; 311} 312 313//===----------------------------------------------------------------------===// 314// Conditional Branch Instructions 315//===----------------------------------------------------------------------===// 316class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> : 317 TA<op, flags, (outs), 318 (ins GPR:$a, GPR:$b), 319 !strconcat(instr_asm, " $a, $b"), 320 [], IIC_BRc> { 321 let rd = br; 322 let Form = FCRR; 323} 324 325class BranchCI<bits<6> op, bits<5> br, string instr_asm> : 326 TB<op, (outs), (ins GPR:$a, brtarget:$offset), 327 !strconcat(instr_asm, " $a, $offset"), 328 [], IIC_BRc> { 329 let rd = br; 330 let Form = FCRI; 331} 332 333//===----------------------------------------------------------------------===// 334// MBlaze arithmetic instructions 335//===----------------------------------------------------------------------===// 336 337let isCommutable = 1, isAsCheapAsAMove = 1 in { 338 def ADDK : Arith<0x04, 0x000, "addk ", add, IIC_ALU>; 339 def AND : Logic<0x21, 0x000, "and ", and>; 340 def OR : Logic<0x20, 0x000, "or ", or>; 341 def XOR : Logic<0x22, 0x000, "xor ", xor>; 342 343 let Predicates=[HasPatCmp] in { 344 def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">; 345 def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">; 346 def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">; 347 } 348 349 let Defs = [CARRY] in { 350 def ADD : Arith<0x00, 0x000, "add ", addc, IIC_ALU>; 351 352 let Uses = [CARRY] in { 353 def ADDC : Arith<0x02, 0x000, "addc ", adde, IIC_ALU>; 354 } 355 } 356 357 let Uses = [CARRY] in { 358 def ADDKC : ArithN<0x06, 0x000, "addkc ", IIC_ALU>; 359 } 360} 361 362let isAsCheapAsAMove = 1 in { 363 def ANDN : ArithN<0x23, 0x000, "andn ", IIC_ALU>; 364 def CMP : ArithN<0x05, 0x001, "cmp ", IIC_ALU>; 365 def CMPU : ArithN<0x05, 0x003, "cmpu ", IIC_ALU>; 366 def RSUBK : ArithR<0x05, 0x000, "rsubk ", sub, IIC_ALU>; 367 368 let Defs = [CARRY] in { 369 def RSUB : ArithR<0x01, 0x000, "rsub ", subc, IIC_ALU>; 370 371 let Uses = [CARRY] in { 372 def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIC_ALU>; 373 } 374 } 375 376 let Uses = [CARRY] in { 377 def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIC_ALU>; 378 } 379} 380 381let isCommutable = 1, Predicates=[HasMul] in { 382 def MUL : Arith<0x10, 0x000, "mul ", mul, IIC_ALUm>; 383} 384 385let isCommutable = 1, Predicates=[HasMul,HasMul64] in { 386 def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIC_ALUm>; 387 def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIC_ALUm>; 388} 389 390let Predicates=[HasMul,HasMul64] in { 391 def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIC_ALUm>; 392} 393 394let Predicates=[HasBarrel] in { 395 def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIC_SHT>; 396 def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIC_SHT>; 397 def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIC_SHT>; 398 def BSRLI : ShiftI<0x19, 0x0, "bsrli ", srl, uimm5, immZExt5>; 399 def BSRAI : ShiftI<0x19, 0x1, "bsrai ", sra, uimm5, immZExt5>; 400 def BSLLI : ShiftI<0x19, 0x2, "bslli ", shl, uimm5, immZExt5>; 401} 402 403let Predicates=[HasDiv] in { 404 def IDIV : ArithR<0x12, 0x000, "idiv ", sdiv, IIC_ALUd>; 405 def IDIVU : ArithR<0x12, 0x002, "idivu ", udiv, IIC_ALUd>; 406} 407 408//===----------------------------------------------------------------------===// 409// MBlaze immediate mode arithmetic instructions 410//===----------------------------------------------------------------------===// 411 412let isAsCheapAsAMove = 1 in { 413 def ADDIK : ArithI<0x0C, "addik ", add, simm16, immSExt16>; 414 def RSUBIK : ArithRI<0x0D, "rsubik ", sub, simm16, immSExt16>; 415 def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>; 416 def ANDI : LogicI<0x29, "andi ", and>; 417 def ORI : LogicI<0x28, "ori ", or>; 418 def XORI : LogicI<0x2A, "xori ", xor>; 419 420 let Defs = [CARRY] in { 421 def ADDI : ArithI<0x08, "addi ", addc, simm16, immSExt16>; 422 def RSUBI : ArithRI<0x09, "rsubi ", subc, simm16, immSExt16>; 423 424 let Uses = [CARRY] in { 425 def ADDIC : ArithI<0x0A, "addic ", adde, simm16, immSExt16>; 426 def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>; 427 } 428 } 429 430 let Uses = [CARRY] in { 431 def ADDIKC : ArithNI<0x0E, "addikc ", simm16, immSExt16>; 432 def RSUBIKC : ArithRNI<0x0F, "rsubikc", simm16, immSExt16>; 433 } 434} 435 436let Predicates=[HasMul] in { 437 def MULI : ArithI<0x18, "muli ", mul, simm16, immSExt16>; 438} 439 440//===----------------------------------------------------------------------===// 441// MBlaze memory access instructions 442//===----------------------------------------------------------------------===// 443 444let canFoldAsLoad = 1, isReMaterializable = 1 in { 445 def LBU : LoadM<0x30, 0x000, "lbu ">; 446 def LBUR : LoadM<0x30, 0x200, "lbur ">; 447 448 def LHU : LoadM<0x31, 0x000, "lhu ">; 449 def LHUR : LoadM<0x31, 0x200, "lhur ">; 450 451 def LW : LoadM<0x32, 0x000, "lw ">; 452 def LWR : LoadM<0x32, 0x200, "lwr ">; 453 454 let Defs = [CARRY] in { 455 def LWX : LoadM<0x32, 0x400, "lwx ">; 456 } 457 458 def LBUI : LoadMI<0x38, "lbui ", zextloadi8>; 459 def LHUI : LoadMI<0x39, "lhui ", zextloadi16>; 460 def LWI : LoadMI<0x3A, "lwi ", load>; 461} 462 463def SB : StoreM<0x34, 0x000, "sb ">; 464def SBR : StoreM<0x34, 0x200, "sbr ">; 465 466def SH : StoreM<0x35, 0x000, "sh ">; 467def SHR : StoreM<0x35, 0x200, "shr ">; 468 469def SW : StoreM<0x36, 0x000, "sw ">; 470def SWR : StoreM<0x36, 0x200, "swr ">; 471 472let Defs = [CARRY] in { 473 def SWX : StoreM<0x36, 0x400, "swx ">; 474} 475 476def SBI : StoreMI<0x3C, "sbi ", truncstorei8>; 477def SHI : StoreMI<0x3D, "shi ", truncstorei16>; 478def SWI : StoreMI<0x3E, "swi ", store>; 479 480//===----------------------------------------------------------------------===// 481// MBlaze branch instructions 482//===----------------------------------------------------------------------===// 483 484let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in { 485 def BRI : BranchI<0x2E, 0x00, "bri ">; 486 def BRAI : BranchI<0x2E, 0x08, "brai ">; 487} 488 489let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { 490 def BEQI : BranchCI<0x2F, 0x00, "beqi ">; 491 def BNEI : BranchCI<0x2F, 0x01, "bnei ">; 492 def BLTI : BranchCI<0x2F, 0x02, "blti ">; 493 def BLEI : BranchCI<0x2F, 0x03, "blei ">; 494 def BGTI : BranchCI<0x2F, 0x04, "bgti ">; 495 def BGEI : BranchCI<0x2F, 0x05, "bgei ">; 496} 497 498let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1, 499 isBarrier = 1 in { 500 def BR : Branch<0x26, 0x00, 0x000, "br ">; 501 def BRA : Branch<0x26, 0x08, 0x000, "bra ">; 502} 503 504let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in { 505 def BEQ : BranchC<0x27, 0x00, 0x000, "beq ">; 506 def BNE : BranchC<0x27, 0x01, 0x000, "bne ">; 507 def BLT : BranchC<0x27, 0x02, 0x000, "blt ">; 508 def BLE : BranchC<0x27, 0x03, 0x000, "ble ">; 509 def BGT : BranchC<0x27, 0x04, 0x000, "bgt ">; 510 def BGE : BranchC<0x27, 0x05, 0x000, "bge ">; 511} 512 513let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1, 514 isBarrier = 1 in { 515 def BRID : BranchI<0x2E, 0x10, "brid ">; 516 def BRAID : BranchI<0x2E, 0x18, "braid ">; 517} 518 519let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in { 520 def BEQID : BranchCI<0x2F, 0x10, "beqid ">; 521 def BNEID : BranchCI<0x2F, 0x11, "bneid ">; 522 def BLTID : BranchCI<0x2F, 0x12, "bltid ">; 523 def BLEID : BranchCI<0x2F, 0x13, "bleid ">; 524 def BGTID : BranchCI<0x2F, 0x14, "bgtid ">; 525 def BGEID : BranchCI<0x2F, 0x15, "bgeid ">; 526} 527 528let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, 529 hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in { 530 def BRD : Branch<0x26, 0x10, 0x000, "brd ">; 531 def BRAD : Branch<0x26, 0x18, 0x000, "brad ">; 532} 533 534let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, 535 hasDelaySlot = 1, hasCtrlDep = 1 in { 536 def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ">; 537 def BNED : BranchC<0x27, 0x11, 0x000, "bned ">; 538 def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ">; 539 def BLED : BranchC<0x27, 0x13, 0x000, "bled ">; 540 def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ">; 541 def BGED : BranchC<0x27, 0x15, 0x000, "bged ">; 542} 543 544let isCall =1, hasDelaySlot = 1, 545 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,CARRY], 546 Uses = [R1] in { 547 def BRLID : BranchLI<0x2E, 0x14, "brlid ">; 548 def BRALID : BranchLI<0x2E, 0x1C, "bralid ">; 549} 550 551let isCall = 1, hasDelaySlot = 1, 552 Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,CARRY], 553 Uses = [R1] in { 554 def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">; 555 def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">; 556} 557 558let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, 559 rd=0x10, Form=FCRI in { 560 def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), 561 "rtsd $target, $imm", 562 [], 563 IIC_BR>; 564} 565 566let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, 567 rd=0x11, Form=FCRI in { 568 def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), 569 "rtid $target, $imm", 570 [], 571 IIC_BR>; 572} 573 574let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, 575 rd=0x12, Form=FCRI in { 576 def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), 577 "rtbd $target, $imm", 578 [], 579 IIC_BR>; 580} 581 582let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, 583 rd=0x14, Form=FCRI in { 584 def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm), 585 "rted $target, $imm", 586 [], 587 IIC_BR>; 588} 589 590//===----------------------------------------------------------------------===// 591// MBlaze misc instructions 592//===----------------------------------------------------------------------===// 593 594let neverHasSideEffects = 1 in { 595 def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIC_ALU>; 596} 597 598let usesCustomInserter = 1 in { 599 def Select_CC : MBlazePseudo<(outs GPR:$dst), 600 (ins GPR:$T, GPR:$F, GPR:$CMP, i32imm:$CC), // F T reversed 601 "; SELECT_CC PSEUDO!", 602 []>; 603 604 def ShiftL : MBlazePseudo<(outs GPR:$dst), 605 (ins GPR:$L, GPR:$R), 606 "; ShiftL PSEUDO!", 607 []>; 608 609 def ShiftRA : MBlazePseudo<(outs GPR:$dst), 610 (ins GPR:$L, GPR:$R), 611 "; ShiftRA PSEUDO!", 612 []>; 613 614 def ShiftRL : MBlazePseudo<(outs GPR:$dst), 615 (ins GPR:$L, GPR:$R), 616 "; ShiftRL PSEUDO!", 617 []>; 618} 619 620let rb = 0 in { 621 def SEXT16 : TA<0x24, 0x061, (outs GPR:$dst), (ins GPR:$src), 622 "sext16 $dst, $src", [], IIC_ALU>; 623 def SEXT8 : TA<0x24, 0x060, (outs GPR:$dst), (ins GPR:$src), 624 "sext8 $dst, $src", [], IIC_ALU>; 625 let Defs = [CARRY] in { 626 def SRL : TA<0x24, 0x041, (outs GPR:$dst), (ins GPR:$src), 627 "srl $dst, $src", [], IIC_ALU>; 628 def SRA : TA<0x24, 0x001, (outs GPR:$dst), (ins GPR:$src), 629 "sra $dst, $src", [], IIC_ALU>; 630 let Uses = [CARRY] in { 631 def SRC : TA<0x24, 0x021, (outs GPR:$dst), (ins GPR:$src), 632 "src $dst, $src", [], IIC_ALU>; 633 } 634 } 635} 636 637let isCodeGenOnly=1 in { 638 def ADDIK32 : ArithI32<0x08, "addik ", simm16, immSExt16>; 639 def ORI32 : LogicI32<0x28, "ori ">; 640 def BRLID32 : BranchLI<0x2E, 0x14, "brlid ">; 641} 642 643//===----------------------------------------------------------------------===// 644// Misc. instructions 645//===----------------------------------------------------------------------===// 646let Form=FRCS in { 647 def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src), 648 "mfs $dst, $src", [], IIC_ALU>; 649} 650 651let Form=FCRCS in { 652 def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src), 653 "mts $dst, $src", [], IIC_ALU>; 654} 655 656def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set), 657 "msrset $dst, $set", [], IIC_ALU>; 658 659def MSRCLR : MSR<0x25, 0x22, (outs GPR:$dst), (ins uimm15:$clr), 660 "msrclr $dst, $clr", [], IIC_ALU>; 661 662let rd=0x0, Form=FCRR in { 663 def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b), 664 "wdc $a, $b", [], IIC_WDC>; 665 def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b), 666 "wdc.flush $a, $b", [], IIC_WDC>; 667 def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b), 668 "wdc.clear $a, $b", [], IIC_WDC>; 669 def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b), 670 "wic $a, $b", [], IIC_WDC>; 671} 672 673def BRK : BranchL<0x26, 0x0C, 0x000, "brk ">; 674def BRKI : BranchLI<0x2E, 0x0C, "brki ">; 675 676def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm), 677 "imm $imm", [], IIC_ALU>; 678 679//===----------------------------------------------------------------------===// 680// Pseudo instructions for atomic operations 681//===----------------------------------------------------------------------===// 682let usesCustomInserter=1 in { 683 def CAS32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$cmp, GPR:$swp), 684 "# atomic compare and swap", 685 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$cmp, GPR:$swp))]>; 686 687 def SWP32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$swp), 688 "# atomic swap", 689 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$swp))]>; 690 691 def LAA32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), 692 "# atomic load and add", 693 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$val))]>; 694 695 def LAS32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), 696 "# atomic load and sub", 697 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$val))]>; 698 699 def LAD32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), 700 "# atomic load and and", 701 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$val))]>; 702 703 def LAO32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), 704 "# atomic load and or", 705 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$val))]>; 706 707 def LAX32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), 708 "# atomic load and xor", 709 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$val))]>; 710 711 def LAN32 : MBlazePseudo<(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), 712 "# atomic load and nand", 713 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$val))]>; 714 715 def MEMBARRIER : MBlazePseudo<(outs), (ins), 716 "# memory barrier", 717 [(membarrier (i32 imm), (i32 imm), (i32 imm), (i32 imm), (i32 imm))]>; 718} 719 720//===----------------------------------------------------------------------===// 721// Arbitrary patterns that map to one or more instructions 722//===----------------------------------------------------------------------===// 723 724// Small immediates 725def : Pat<(i32 0), (ADDK (i32 R0), (i32 R0))>; 726def : Pat<(i32 immSExt16:$imm), (ADDIK (i32 R0), imm:$imm)>; 727def : Pat<(i32 immZExt16:$imm), (ORI (i32 R0), imm:$imm)>; 728 729// Arbitrary immediates 730def : Pat<(i32 imm:$imm), (ADDIK (i32 R0), imm:$imm)>; 731 732// In register sign extension 733def : Pat<(sext_inreg GPR:$src, i16), (SEXT16 GPR:$src)>; 734def : Pat<(sext_inreg GPR:$src, i8), (SEXT8 GPR:$src)>; 735 736// Call 737def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)), 738 (BRLID (i32 R15), tglobaladdr:$dst)>; 739 740def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)), 741 (BRLID (i32 R15), texternalsym:$dst)>; 742 743def : Pat<(MBlazeJmpLink GPR:$dst), 744 (BRALD (i32 R15), GPR:$dst)>; 745 746// Shift Instructions 747def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>; 748def : Pat<(sra GPR:$L, GPR:$R), (ShiftRA GPR:$L, GPR:$R)>; 749def : Pat<(srl GPR:$L, GPR:$R), (ShiftRL GPR:$L, GPR:$R)>; 750 751// SET_CC operations 752def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), 753 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 754 (CMP GPR:$R, GPR:$L), 1)>; 755def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), 756 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 757 (CMP GPR:$R, GPR:$L), 2)>; 758def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), 759 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 760 (CMP GPR:$R, GPR:$L), 3)>; 761def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), 762 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 763 (CMP GPR:$R, GPR:$L), 4)>; 764def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), 765 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 766 (CMP GPR:$R, GPR:$L), 5)>; 767def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), 768 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 769 (CMP GPR:$R, GPR:$L), 6)>; 770def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), 771 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 772 (CMPU GPR:$R, GPR:$L), 3)>; 773def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), 774 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 775 (CMPU GPR:$R, GPR:$L), 4)>; 776def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), 777 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 778 (CMPU GPR:$R, GPR:$L), 5)>; 779def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), 780 (Select_CC (ADDIK (i32 R0), 1), (ADDIK (i32 R0), 0), 781 (CMPU GPR:$R, GPR:$L), 6)>; 782 783// SELECT operations 784def : Pat<(select (i32 GPR:$C), (i32 GPR:$T), (i32 GPR:$F)), 785 (Select_CC GPR:$T, GPR:$F, GPR:$C, 2)>; 786 787// SELECT_CC 788def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 789 (i32 GPR:$T), (i32 GPR:$F), SETEQ), 790 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 1)>; 791def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 792 (i32 GPR:$T), (i32 GPR:$F), SETNE), 793 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 2)>; 794def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 795 (i32 GPR:$T), (i32 GPR:$F), SETGT), 796 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 3)>; 797def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 798 (i32 GPR:$T), (i32 GPR:$F), SETLT), 799 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 4)>; 800def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 801 (i32 GPR:$T), (i32 GPR:$F), SETGE), 802 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 5)>; 803def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 804 (i32 GPR:$T), (i32 GPR:$F), SETLE), 805 (Select_CC GPR:$T, GPR:$F, (CMP GPR:$R, GPR:$L), 6)>; 806def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 807 (i32 GPR:$T), (i32 GPR:$F), SETUGT), 808 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 3)>; 809def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 810 (i32 GPR:$T), (i32 GPR:$F), SETULT), 811 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 4)>; 812def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 813 (i32 GPR:$T), (i32 GPR:$F), SETUGE), 814 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 5)>; 815def : Pat<(selectcc (i32 GPR:$L), (i32 GPR:$R), 816 (i32 GPR:$T), (i32 GPR:$F), SETULE), 817 (Select_CC GPR:$T, GPR:$F, (CMPU GPR:$R, GPR:$L), 6)>; 818 819// Ret instructions 820def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>; 821def : Pat<(MBlazeIRet GPR:$target), (RTID GPR:$target, 0x0)>; 822 823// BR instructions 824def : Pat<(br bb:$T), (BRID bb:$T)>; 825def : Pat<(brind GPR:$T), (BRAD GPR:$T)>; 826 827// BRCOND instructions 828def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T), 829 (BEQID (CMP GPR:$R, GPR:$L), bb:$T)>; 830def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T), 831 (BNEID (CMP GPR:$R, GPR:$L), bb:$T)>; 832def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGT), bb:$T), 833 (BGTID (CMP GPR:$R, GPR:$L), bb:$T)>; 834def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLT), bb:$T), 835 (BLTID (CMP GPR:$R, GPR:$L), bb:$T)>; 836def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), bb:$T), 837 (BGEID (CMP GPR:$R, GPR:$L), bb:$T)>; 838def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETLE), bb:$T), 839 (BLEID (CMP GPR:$R, GPR:$L), bb:$T)>; 840def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), bb:$T), 841 (BGTID (CMPU GPR:$R, GPR:$L), bb:$T)>; 842def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), bb:$T), 843 (BLTID (CMPU GPR:$R, GPR:$L), bb:$T)>; 844def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), bb:$T), 845 (BGEID (CMPU GPR:$R, GPR:$L), bb:$T)>; 846def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), bb:$T), 847 (BLEID (CMPU GPR:$R, GPR:$L), bb:$T)>; 848def : Pat<(brcond (i32 GPR:$C), bb:$T), 849 (BNEID GPR:$C, bb:$T)>; 850 851// Jump tables, global addresses, and constant pools 852def : Pat<(MBWrapper tglobaladdr:$in), (ORI (i32 R0), tglobaladdr:$in)>; 853def : Pat<(MBWrapper tjumptable:$in), (ORI (i32 R0), tjumptable:$in)>; 854def : Pat<(MBWrapper tconstpool:$in), (ORI (i32 R0), tconstpool:$in)>; 855 856// Misc instructions 857def : Pat<(and (i32 GPR:$lh), (not (i32 GPR:$rh))),(ANDN GPR:$lh, GPR:$rh)>; 858 859// Convert any extend loads into zero extend loads 860def : Pat<(extloadi8 iaddr:$src), (i32 (LBUI iaddr:$src))>; 861def : Pat<(extloadi16 iaddr:$src), (i32 (LHUI iaddr:$src))>; 862def : Pat<(extloadi8 xaddr:$src), (i32 (LBU xaddr:$src))>; 863def : Pat<(extloadi16 xaddr:$src), (i32 (LHU xaddr:$src))>; 864 865// 32-bit load and store 866def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>; 867def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>; 868 869// 16-bit load and store 870def : Pat<(truncstorei16 (i32 GPR:$dst), xaddr:$addr), (SH GPR:$dst, xaddr:$addr)>; 871def : Pat<(zextloadi16 xaddr:$addr), (i32 (LHU xaddr:$addr))>; 872 873// 8-bit load and store 874def : Pat<(truncstorei8 (i32 GPR:$dst), xaddr:$addr), (SB GPR:$dst, xaddr:$addr)>; 875def : Pat<(zextloadi8 xaddr:$addr), (i32 (LBU xaddr:$addr))>; 876 877// Peepholes 878def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>; 879 880//===----------------------------------------------------------------------===// 881// Floating Point Support 882//===----------------------------------------------------------------------===// 883include "MBlazeInstrFSL.td" 884include "MBlazeInstrFPU.td" 885