| /external/llvm/lib/Target/ARM/ |
| D | ARMMCCodeEmitter.cpp | 77 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
80 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
86 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
91 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
118 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
|
| D | ARMCodeEmitter.cpp | 103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue()
157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
247 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStmModeOpValue()
249 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStSORegOpValue()
289 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OpValue()
291 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OffsetOpValue()
293 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode3OffsetOpValue()
1004 unsigned OpIdx) { in getMachineSoRegOpValue() argument
1007 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); in getMachineSoRegOpValue()
[all …]
|
| D | ARMExpandPseudoInsts.cpp | 414 unsigned OpIdx = 0; in ExpandVLD() local
416 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
417 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
428 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
431 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
432 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
442 SrcOpIdx = OpIdx++; in ExpandVLD()
445 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
446 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
|
| D | ARMBaseInstrInfo.cpp | 1782 unsigned OpIdx = Commute ? 2 : 1; in FoldImmediate() local
1783 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate()
1784 bool isKill = UseMI->getOperand(OpIdx).isKill(); in FoldImmediate()
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassemblerCore.cpp | 596 unsigned &OpIdx = NumOpsAdded; in DisassembleMulFrm() local
598 OpIdx = 0; in DisassembleMulFrm()
617 ++OpIdx; in DisassembleMulFrm()
629 OpIdx += 3; in DisassembleMulFrm()
633 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) { in DisassembleMulFrm()
636 ++OpIdx; in DisassembleMulFrm()
700 unsigned &OpIdx = NumOpsAdded; in DisassembleCoprocessor() local
721 OpIdx = 0; in DisassembleCoprocessor()
726 ++OpIdx; in DisassembleCoprocessor()
729 ++OpIdx; in DisassembleCoprocessor()
[all …]
|
| D | ThumbDisassemblerCore.h | 354 unsigned &OpIdx = NumOpsAdded; in DisassembleThumb1General() local
356 OpIdx = 0; in DisassembleThumb1General()
371 ++OpIdx; in DisassembleThumb1General()
374 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) { in DisassembleThumb1General()
375 assert(OpInfo[OpIdx].isOptionalDef() && "Optional def operand expected"); in DisassembleThumb1General()
377 ++OpIdx; in DisassembleThumb1General()
381 assert(OpIdx < NumOps && "More operands expected"); in DisassembleThumb1General()
382 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) { in DisassembleThumb1General()
387 ++OpIdx; in DisassembleThumb1General()
391 if (OpIdx == NumOps) in DisassembleThumb1General()
[all …]
|
| /external/llvm/include/llvm/Analysis/ |
| D | ConstantsScanner.h | 28 unsigned OpIdx; // Operand index variable
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() && in isAtConstant()
35 return isa<Constant>(InstI->getOperand(OpIdx)); in isAtConstant()
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) { in constant_iterator()
47 : InstI(inst_end(F)), OpIdx(0) { in constant_iterator()
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant()) {
65 ++OpIdx;
[all …]
|
| /external/llvm/utils/TableGen/ |
| D | CodeEmitterGen.cpp | 103 unsigned OpIdx; in AddCodeToMergeInOperand() local
104 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
106 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
107 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
114 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
128 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
135 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
|
| D | CodeGenInstruction.cpp | 135 unsigned OpIdx; in getOperandNamed() local
136 if (hasOperandNamed(Name, OpIdx)) return OpIdx; in getOperandNamed()
144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { in hasOperandNamed()
148 OpIdx = i; in hasOperandNamed()
171 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local
175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && in ParseOperandName()
181 return std::make_pair(OpIdx, 0U); in ParseOperandName()
185 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName()
192 return std::make_pair(OpIdx, i); in ParseOperandName()
|
| D | CodeGenInstruction.h | 161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
|
| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 49 unsigned Reg, unsigned OpIdx, in CanTurnIntoImplicitDef() argument
51 switch(OpIdx) { in CanTurnIntoImplicitDef()
257 unsigned OpIdx = Ops[j]; in runOnMachineFunction() local
258 RMI->RemoveOperand(OpIdx-j); in runOnMachineFunction()
|
| D | MachineInstr.cpp | 1566 unsigned OpIdx = DeadOps.back(); in addRegisterKilled() local
1567 if (getOperand(OpIdx).isImplicit()) in addRegisterKilled()
1568 RemoveOperand(OpIdx); in addRegisterKilled()
1570 getOperand(OpIdx).setIsKill(false); in addRegisterKilled()
1618 unsigned OpIdx = DeadOps.back(); in addRegisterDead() local
1619 if (getOperand(OpIdx).isImplicit()) in addRegisterDead()
1620 RemoveOperand(OpIdx); in addRegisterDead()
1622 getOperand(OpIdx).setIsDead(false); in addRegisterDead()
|
| D | DwarfEHPrepare.cpp | 188 unsigned OpIdx = Sel->getNumArgOperands() - 1; in CleanupSelectors() local
189 GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx)); in CleanupSelectors()
191 Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer()); in CleanupSelectors()
|
| D | LiveIntervalAnalysis.cpp | 1043 unsigned OpIdx = Ops[i]; in FilterFoldedOps() local
1044 MachineOperand &MO = MI->getOperand(OpIdx); in FilterFoldedOps()
1052 if (MI->isRegTiedToDefOperand(OpIdx)) { in FilterFoldedOps()
1058 FoldOps.push_back(OpIdx); in FilterFoldedOps()
|
| D | RegisterCoalescer.cpp | 600 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); in RemoveCopyByCommutingDef() local
601 NewMI->getOperand(OpIdx).setIsKill(); in RemoveCopyByCommutingDef()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeMCCodeEmitter.cpp | 49 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const { in getMachineOpValue()
50 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ProcessImplicitDefs.h | 34 unsigned OpIdx,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 104 unsigned OpIdx, SDep& dep) const;
|
| D | ScheduleDAGSDNodes.cpp | 579 unsigned OpIdx, SDep& dep) const{ in ComputeOperandLatency() argument
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in ComputeOperandLatency()
590 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in ComputeOperandLatency()
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in ComputeOperandLatency()
|
| D | LegalizeVectorTypes.cpp | 1397 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { in WidenVecRes_Binary() local
1399 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); in WidenVecRes_Binary()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4114 int OpIdx, int NumElems, unsigned &OpNum) { in isShuffleMaskConsecutive() argument
4118 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { in isShuffleMaskConsecutive()
4130 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) in isShuffleMaskConsecutive()
|