| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
[all …]
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| D | SystemZInstrInfo.td | 71 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
74 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
79 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
83 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
96 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
104 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
[all …]
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| D | SystemZInstrFormats.td | 17 def Pseudo : Format<0>;
125 // Pseudo instructions
128 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
129 : InstSystemZ<0, Pseudo, outs, ins> {
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
89 def VAARG_64 : I<0, Pseudo,
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
114 // EH Pseudo Instructions
[all …]
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| D | X86InstrInfo.h | 259 Pseudo = 0, enumerator
545 case X86II::Pseudo: in getMemoryOperandNo()
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| D | X86InstrFormats.td | 21 def Pseudo : Format<0>; def RawFrm : Format<1>;
133 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
176 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {
230 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
232 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
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| D | X86MCCodeEmitter.cpp | 810 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) in EncodeInstruction()
859 case X86II::Pseudo: in EncodeInstruction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 65 // Pseudo valuetype mapped to the current pointer size to any address space.
69 // Pseudo valuetype to represent "vector of any size"
72 // Pseudo valuetype to represent "float of any format"
75 // Pseudo valuetype to represent "integer of any bit width"
78 // Pseudo valuetype mapped to the current pointer size.
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 360 // Pseudo-instructions:
364 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
366 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
375 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
389 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
392 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
395 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
[all …]
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| D | PPCInstr64Bit.td | 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
134 def ATOMIC_LOAD_ADD_I64 : Pseudo<
137 def ATOMIC_LOAD_SUB_I64 : Pseudo<
140 def ATOMIC_LOAD_OR_I64 : Pseudo<
143 def ATOMIC_LOAD_XOR_I64 : Pseudo<
146 def ATOMIC_LOAD_AND_I64 : Pseudo<
149 def ATOMIC_LOAD_NAND_I64 : Pseudo<
153 def ATOMIC_CMP_SWAP_I64 : Pseudo<
158 def ATOMIC_SWAP_I64 : Pseudo<
176 def TCRETURNdi8 :Pseudo< (outs),
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 207 // Pseudo instructions.
208 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
213 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
217 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
220 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
242 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
244 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
247 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
263 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
[all …]
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| D | SparcInstrInfo.h | 30 Pseudo = (1<<0), enumerator
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| /external/chromium/third_party/libjingle/source/ |
| D | CHANGELOG | 45 - Pseudo-TCP support provides TCP-like reliability over a P2PSocket
47 using Pseudo-TCP.
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| /external/llvm/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.td | 132 // Pseudo instructions.
133 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
137 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
140 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
203 // Pseudo-instruction for loading a general 32-bit constant.
204 def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src),
208 def LOAD32sym: Pseudo<(outs GR:$dst), (ins i32imm:$src),
234 // Pseudo-instruction for loading a stack slot
235 def LOAD32fi: Pseudo<(outs DP:$dst), (ins MEMii:$mem),
240 def LOAD16fi: Pseudo<(outs D16:$dst), (ins MEMii:$mem),
[all …]
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| /external/llvm/utils/TableGen/ |
| D | PseudoLoweringEmitter.h | 54 void evaluateExpansion(Record *Pseudo);
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| D | X86RecognizableInstr.cpp | 44 Pseudo = 0, enumerator
344 if (Form == X86Local::Pseudo || in filter()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
[all …]
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| D | MSP430InstrFormats.td | 206 // Pseudo instructions
207 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 153 // Pseudo 256-bit registers to represent pairs of Q registers. These should
172 // Pseudo 512-bit registers to represent four consecutive Q registers.
302 // Pseudo 256-bit vector register class to model pairs of Q registers
320 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
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| D | ARMBaseInstrInfo.h | 55 Pseudo = 0 << FormShift, enumerator
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUInstrFormats.td | 288 // Pseudo instructions, like call frames:
291 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 45 // Mips Pseudo Instructions Format
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 48 def Pseudo : Format<0>; def RawFrm : Format<1>;
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFormats.td | 81 // Pseudo instruction class
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| /external/llvm/lib/Target/Alpha/ |
| D | AlphaInstrFormats.td | 261 // Pseudo instructions.
|