| /external/openssl/crypto/sha/asm/ |
| D | sha512-armv4.s | 106 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
158 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
201 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
216 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
246 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
298 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
|
| /external/openssl/crypto/sha/ |
| D | sha512.c | 353 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro
383 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro
391 # define ROTR(a,n) _rotr64((a),n) macro
426 #ifndef ROTR
427 #define ROTR(x,s) (((x)>>s) | (x)<<(64-s)) macro
430 #define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
431 #define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
432 #define sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
433 #define sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMAddressingModes.h | 69 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 155 case ISD::ROTR: in LegalizeOp()
|
| D | DAGCombiner.cpp | 2725 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) in MatchBSwapHWord()
2726 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); in MatchBSwapHWord()
2902 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); in MatchRotate()
2947 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); in MatchRotate()
2984 return DAG.getNode(ISD::ROTR, DL, VT, in MatchRotate()
2998 return DAG.getNode(ISD::ROTR, DL, VT, in MatchRotate()
3027 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
3041 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, in MatchRotate()
|
| D | SelectionDAG.cpp | 2161 case ISD::ROTR: in ComputeNumSignBits()
2166 if (Op.getOpcode() == ISD::ROTR) in ComputeNumSignBits()
2645 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); in FoldConstantArithmetic()
2747 case ISD::ROTR: in getNode()
5886 case ISD::ROTR: return "rotr"; in getOperationName()
6347 case ISD::ROTR: in UnrollVectorOp()
|
| D | LegalizeIntegerTypes.cpp | 740 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; in PromoteIntegerOperand()
2365 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; in ExpandIntegerOperand()
|
| D | LegalizeDAG.cpp | 926 case ISD::ROTR: in LegalizeOp()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 104 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
106 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 234 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/); in SPUTargetLowering()
235 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/); in SPUTargetLowering()
236 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/); in SPUTargetLowering()
2219 case ISD::ROTR: in LowerI8Math()
2803 case ISD::ROTR: in LowerOperation()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 164 setOperationAction(ISD::ROTR, MVT::i32, Expand); in MBlazeTargetLowering()
|
| /external/llvm/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 94 setOperationAction(ISD::ROTR , MVT::i64, Expand); in AlphaTargetLowering()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 766 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 517 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
|
| D | MipsISelLowering.cpp | 132 setOperationAction(ISD::ROTR, MVT::i32, Expand); in MipsTargetLowering()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 110 setOperationAction(ISD::ROTR , MVT::i32, Expand); in XCoreTargetLowering()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 321 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 155 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
156 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 740 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
|