| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 211 // All calls clobber the non-callee saved registers. RSP is marked as
220 Uses = [RSP] in {
243 // All calls clobber the non-callee saved registers. RSP is marked as
251 Uses = [RSP] in {
268 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
269 let Defs = [RAX, R10, R11, RSP, EFLAGS],
270 Uses = [RSP] in {
284 Uses = [RSP],
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| D | X86CompilationCallback_Win64.asm | 20 ; Save RSP.
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| D | X86RegisterInfo.cpp | 69 StackPtr = X86::RSP; in X86RegisterInfo()
371 Reserved.set(X86::RSP); in getReservedRegs()
672 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
709 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
745 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
781 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
782 return X86::RSP; in getX86SubSuperRegister()
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| D | X86RegisterInfo.td | 131 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> {
387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> {
398 // GR64_NOSP - GR64 registers except RSP (and RIP).
399 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)> {
413 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
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| D | X86InstrInfo.td | 234 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
618 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
668 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
683 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
692 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
695 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
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| D | X86InstrCompiler.td | 56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
292 // All calls clobber the non-callee saved registers. RSP is marked as
300 Uses = [RSP] in
321 Uses = [RSP, RDI],
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| D | X86MCCodeEmitter.cpp | 320 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in EmitMemModRMByte()
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| D | X86CodeEmitter.cpp | 536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in emitMemModRMByte()
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| D | X86FastISel.cpp | 61 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; in X86FastISel()
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| D | X86ISelLowering.cpp | 215 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; in X86TargetLowering()
10632 .addReg(X86::RSP, RegState::Implicit) in EmitLoweredWinAlloca()
10634 .addReg(X86::RSP, RegState::Define | RegState::Implicit) in EmitLoweredWinAlloca()
10645 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) in EmitLoweredWinAlloca()
10646 .addReg(X86::RSP) in EmitLoweredWinAlloca()
13134 case X86::SP: DestReg = X86::RSP; break; in getRegForInlineAsmConstraint()
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| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 50 #define RSP 152 macro
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 133 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: in getX86RegNum()
325 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); in createX86MCAsmInfo()
329 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); in createX86MCAsmInfo()
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| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 105 GENOFFSET(AMD64,amd64,RSP); in foo()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 183 ENTRY(RSP) \
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| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-amd64-linux.c | 359 SC2(rsp,RSP); in synth_ucontext()
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| /external/valgrind/main/memcheck/ |
| D | mc_machine.c | 474 if (o == GOF(RSP) && is1248) return o; in get_otrack_shadow_offset_wrk()
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| /external/strace/ |
| D | process.c | 2636 { 8*RSP, "8*RSP" },
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| /external/valgrind/main/exp-ptrcheck/ |
| D | h_main.c | 1409 if (o == GOF(RSP) && is8) goto exactly1; in get_IntRegInfo()
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