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Searched refs:SIGN_EXTEND (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h359 SIGN_EXTEND, enumerator
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp322 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom); in SPUTargetLowering()
447 setTargetDAGCombine(ISD::SIGN_EXTEND); in SPUTargetLowering()
722 result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result); in LowerLOAD()
2203 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2204 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); in LowerI8Math()
2214 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2215 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); in LowerI8Math()
2264 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2266 unsigned N1Opc = ISD::SIGN_EXTEND; in LowerI8Math()
2279 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp712 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1078 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
1150 case ISD::SIGN_EXTEND: in combine()
1468 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADD()
1470 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { in visitADD()
2006 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
2007 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
2124 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); in visitSMUL_LOHI()
2125 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); in visitSMUL_LOHI()
2224 N0.getOpcode() == ISD::SIGN_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
[all …]
DLegalizeVectorOps.cpp165 case ISD::SIGN_EXTEND: in LegalizeOp()
DFastISel.cpp269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, in getRegForGEPIndex()
627 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); in SelectCall()
951 return SelectCast(I, ISD::SIGN_EXTEND); in SelectOperator()
DLegalizeFloatTypes.cpp553 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in SoftenFloatRes_XINT_TO_FP()
1173 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1180 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1184 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src); in ExpandFloatRes_XINT_TO_FP()
DLegalizeVectorTypes.cpp89 case ISD::SIGN_EXTEND: in ScalarizeVectorResult()
290 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res); in ScalarizeVecRes_VSETCC()
466 case ISD::SIGN_EXTEND: in SplitVectorResult()
988 case ISD::SIGN_EXTEND: in SplitVectorOperand()
1267 case ISD::SIGN_EXTEND: in WidenVectorResult()
2008 case ISD::SIGN_EXTEND: in WidenVectorOperand()
DLegalizeIntegerTypes.cpp88 case ISD::SIGN_EXTEND: in PromoteIntegerResult()
261 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
368 if (N->getOpcode() == ISD::SIGN_EXTEND) in PromoteIntRes_INT_EXTEND()
727 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; in PromoteIntegerOperand()
1051 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
2071 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_SIGN_EXTEND()
DSelectionDAG.cpp881 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : in getSExtOrTrunc()
1859 case ISD::SIGN_EXTEND: { in ComputeMaskedBits()
2095 case ISD::SIGN_EXTEND: in ComputeNumSignBits()
2376 case ISD::SIGN_EXTEND: in getNode()
2471 case ISD::SIGN_EXTEND: in getNode()
2481 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode()
2515 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
2541 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
5925 case ISD::SIGN_EXTEND: return "sign_extend"; in getOperationName()
DLegalizeTypes.cpp1110 ExtendCode = ISD::SIGN_EXTEND; in PromoteTargetBoolean()
DLegalizeDAG.cpp1341 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; in LegalizeOp()
2640 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
3538 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; in ExpandNode()
3876 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
DTargetLowering.cpp1014 ExtendKind = ISD::SIGN_EXTEND; in GetReturnInfo()
1655 case ISD::SIGN_EXTEND: { in SimplifyDemandedBits()
DSelectionDAGBuilder.cpp1170 ExtendKind = ISD::SIGN_EXTEND; in visitRet()
1190 if (ExtendKind == ISD::SIGN_EXTEND) in visitRet()
2600 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); in visitSExt()
6170 ExtendKind = ISD::SIGN_EXTEND; in LowerCallTo()
/external/llvm/lib/Target/Blackfin/
DBlackfinISelLowering.cpp258 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
315 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp120 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
190 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
478 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp415 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
588 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp501 setTargetDAGCombine(ISD::SIGN_EXTEND); in ARMTargetLowering()
1269 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
3007 CastOpc = ISD::SIGN_EXTEND; in LowerVectorINT_TO_FP()
4499 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
4519 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) in SkipExtension()
4652 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
4653 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); in LowerSDIV_v4i8()
4682 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
4683 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); in LowerSDIV_v4i16()
4724 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
[all …]
DARMFastISel.cpp1571 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1593 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp757 ISD::SIGN_EXTEND; in X86SelectRet()
1652 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
1676 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
DX86ISelLowering.cpp754 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
2071 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
11159 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && in PerformEXTRACT_VECTOR_ELTCombine()
11828 case ISD::SIGN_EXTEND: in CMPEQCombine()
12438 case ISD::SIGN_EXTEND: in isTypeDesirableForOp()
12482 case ISD::SIGN_EXTEND: in IsDesirableToPromoteOp()
/external/llvm/lib/Target/MBlaze/
DMBlazeISelLowering.cpp728 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
/external/llvm/lib/Target/Alpha/
DAlphaISelLowering.cpp262 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp421 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp928 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td342 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;

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