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/external/llvm/lib/Target/ARM/
DARMSchedule.td13 def IIC_iALUx : InstrItinClass;
14 def IIC_iALUi : InstrItinClass;
15 def IIC_iALUr : InstrItinClass;
16 def IIC_iALUsi : InstrItinClass;
17 def IIC_iALUsir : InstrItinClass;
18 def IIC_iALUsr : InstrItinClass;
19 def IIC_iBITi : InstrItinClass;
20 def IIC_iBITr : InstrItinClass;
21 def IIC_iBITsi : InstrItinClass;
22 def IIC_iBITsr : InstrItinClass;
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DARMRegisterInfo.td29 def ssub_0 : SubRegIndex;
30 def ssub_1 : SubRegIndex;
31 def ssub_2 : SubRegIndex; // In a Q reg.
32 def ssub_3 : SubRegIndex;
34 def dsub_0 : SubRegIndex;
35 def dsub_1 : SubRegIndex;
36 def dsub_2 : SubRegIndex;
37 def dsub_3 : SubRegIndex;
38 def dsub_4 : SubRegIndex;
39 def dsub_5 : SubRegIndex;
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/external/llvm/lib/Target/PTX/
DPTXRegisterInfo.td25 def P0 : PTXReg<"p0">;
26 def P1 : PTXReg<"p1">;
27 def P2 : PTXReg<"p2">;
28 def P3 : PTXReg<"p3">;
29 def P4 : PTXReg<"p4">;
30 def P5 : PTXReg<"p5">;
31 def P6 : PTXReg<"p6">;
32 def P7 : PTXReg<"p7">;
33 def P8 : PTXReg<"p8">;
34 def P9 : PTXReg<"p9">;
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def IfStmt : Stmt;
16 def SwitchStmt : Stmt;
17 def WhileStmt : Stmt;
18 def DoStmt : Stmt;
19 def ForStmt : Stmt;
20 def GotoStmt : Stmt;
21 def IndirectGotoStmt : Stmt;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def : DiagGroup<"address">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
25 def : DiagGroup<"attributes">;
26 def : DiagGroup<"bad-function-cast">;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def Named : Decl<1>;
15 def Namespace : DDecl<Named>, DeclContext;
16 def UsingDirective : DDecl<Named>;
17 def NamespaceAlias : DDecl<Named>;
18 def Label : DDecl<Named>;
19 def Type : DDecl<Named, 1>;
20 def TypedefName : DDecl<Type, 1>;
21 def Typedef : DDecl<TypedefName>;
22 def TypeAlias : DDecl<TypedefName>;
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Darm_neon.td17 def OP_NONE : Op;
18 def OP_ADD : Op;
19 def OP_ADDL : Op;
20 def OP_ADDW : Op;
21 def OP_SUB : Op;
22 def OP_SUBL : Op;
23 def OP_SUBW : Op;
24 def OP_MUL : Op;
25 def OP_MLA : Op;
26 def OP_MLAL : Op;
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DDiagnosticParseKinds.td16 def w_asm_qualifier_ignored : Warning<"ignored %0 qualifier on asm">,
18 def warn_file_asm_volatile : Warning<
23 def ext_empty_source_file : Extension<"ISO C forbids an empty source file">;
24 def ext_top_level_semi : Extension<
26 def ext_extra_struct_semi : Extension<
28 def ext_extra_ivar_semi : Extension<
31 def auto_storage_class : ExtWarn<
35 def ext_duplicate_declspec : Extension<"duplicate '%0' declaration specifier">;
36 def ext_plain_complex : ExtWarn<
38 def ext_integer_complex : Extension<
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DDiagnosticLexKinds.td16 def null_in_string : Warning<"null character(s) preserved in string literal">;
17 def null_in_char : Warning<"null character(s) preserved in character literal">;
18 def null_in_file : Warning<"null character ignored">;
19 def warn_nested_block_comment : Warning<"'/*' within block comment">,
21 def escaped_newline_block_comment_end : Warning<
24 def backslash_newline_space : Warning<
28 def trigraph_ignored : Warning<"trigraph ignored">, InGroup<Trigraphs>;
29 def trigraph_ignored_block_comment : Warning<
31 def trigraph_ends_block_comment : Warning<"trigraph ends block comment">,
33 def trigraph_converted : Warning<"trigraph converted to '%0' character">,
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/external/llvm/lib/Target/CellSPU/
DSPURegisterInfo.td24 def R0 : SPUVecReg<0, "$lr">, DwarfRegNum<[0]>;
25 def R1 : SPUVecReg<1, "$sp">, DwarfRegNum<[1]>;
26 def R2 : SPUVecReg<2, "$2">, DwarfRegNum<[2]>;
27 def R3 : SPUVecReg<3, "$3">, DwarfRegNum<[3]>;
28 def R4 : SPUVecReg<4, "$4">, DwarfRegNum<[4]>;
29 def R5 : SPUVecReg<5, "$5">, DwarfRegNum<[5]>;
30 def R6 : SPUVecReg<6, "$6">, DwarfRegNum<[6]>;
31 def R7 : SPUVecReg<7, "$7">, DwarfRegNum<[7]>;
32 def R8 : SPUVecReg<8, "$8">, DwarfRegNum<[8]>;
33 def R9 : SPUVecReg<9, "$9">, DwarfRegNum<[9]>;
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/external/llvm/include/llvm/CompilerDriver/
DCommon.td20 def in_language;
21 def out_language;
22 def output_suffix;
23 def command;
24 def out_file_option;
25 def in_file_option;
26 def join;
27 def sink;
28 def works_on_empty;
29 def actions;
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/external/clang/include/clang/Driver/
DOptions.td21 def CompileOnly_Group : OptionGroup<"<CompileOnly group>">;
23 def I_Group : OptionGroup<"<I group>">, Group<CompileOnly_Group>;
24 def M_Group : OptionGroup<"<M group>">, Group<CompileOnly_Group>;
25 def T_Group : OptionGroup<"<T group>">;
26 def O_Group : OptionGroup<"<O group>">, Group<CompileOnly_Group>;
27 def W_Group : OptionGroup<"<W group>">, Group<CompileOnly_Group>;
28 def X_Group : OptionGroup<"<X group>">;
29 def a_Group : OptionGroup<"<a group>">;
30 def d_Group : OptionGroup<"<d group>">;
31 def f_Group : OptionGroup<"<f group>">, Group<CompileOnly_Group>;
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/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td14 def sub_lt : SubRegIndex;
15 def sub_gt : SubRegIndex;
16 def sub_eq : SubRegIndex;
17 def sub_un : SubRegIndex;
18 def sub_32 : SubRegIndex;
68 def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>;
69 def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>;
70 def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>;
71 def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>;
72 def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>;
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td24 def sub_even : SubRegIndex;
25 def sub_odd : SubRegIndex;
45 def ICC : SparcCtrlReg<"ICC">;
46 def FCC : SparcCtrlReg<"FCC">;
49 def Y : SparcCtrlReg<"Y">;
52 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
53 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
54 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
55 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
56 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
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/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td38 def sub_fpeven : SubRegIndex;
39 def sub_fpodd : SubRegIndex;
59 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
60 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
61 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
62 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
63 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
64 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
65 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
66 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
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/external/llvm/include/llvm/
DIntrinsicsPowerPC.td21 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
22 def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], []>;
23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
24 def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
25 def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty], []>;
26 def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;
27 def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
28 def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
31 def int_ppc_sync : Intrinsic<[], [], []>;
88 def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">,
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DIntrinsicsCellSPU.td20 def cell_i7_ty: LLVMType<i8>;
21 def cell_i8_ty: LLVMType<i8>;
24 def llvm_i128_ty : LLVMType<i128>;
103 def int_spu_si_fsmbi : v8i16_u16imm<"fsmbi">;
104 def int_spu_si_ah : v8i16_rr<"ah">;
105 def int_spu_si_ahi : v8i16_s10imm<"ahi">;
106 def int_spu_si_a : v4i32_rr<"a">;
107 def int_spu_si_ai : v4i32_s10imm<"ai">;
108 def int_spu_si_sfh : v8i16_rr<"sfh">;
109 def int_spu_si_sfhi : v8i16_s10imm<"sfhi">;
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DIntrinsicsX86.td17 def int_x86_int : Intrinsic<[], [llvm_i8_ty]>;
24 def int_x86_3dnow_pavgusb : GCCBuiltin<"__builtin_ia32_pavgusb">,
27 def int_x86_3dnow_pf2id : GCCBuiltin<"__builtin_ia32_pf2id">,
29 def int_x86_3dnow_pfacc : GCCBuiltin<"__builtin_ia32_pfacc">,
32 def int_x86_3dnow_pfadd : GCCBuiltin<"__builtin_ia32_pfadd">,
35 def int_x86_3dnow_pfcmpeq : GCCBuiltin<"__builtin_ia32_pfcmpeq">,
38 def int_x86_3dnow_pfcmpge : GCCBuiltin<"__builtin_ia32_pfcmpge">,
41 def int_x86_3dnow_pfcmpgt : GCCBuiltin<"__builtin_ia32_pfcmpgt">,
44 def int_x86_3dnow_pfmax : GCCBuiltin<"__builtin_ia32_pfmax">,
47 def int_x86_3dnow_pfmin : GCCBuiltin<"__builtin_ia32_pfmin">,
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DIntrinsicsXCore.td13 def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
14 def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty],
17 def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],
20 def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
22 def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
24 def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
25 def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
26 def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;
27 def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>;
28 def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>;
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/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td57 def subreg_32bit : SubRegIndex;
58 def subreg_odd32 : SubRegIndex;
59 def subreg_even : SubRegIndex;
60 def subreg_odd : SubRegIndex;
64 def R0W : GPR32< 0, "r0">;
65 def R1W : GPR32< 1, "r1">;
66 def R2W : GPR32< 2, "r2">;
67 def R3W : GPR32< 3, "r3">;
68 def R4W : GPR32< 4, "r4">;
69 def R5W : GPR32< 5, "r5">;
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/external/llvm/lib/Target/Alpha/
DAlphaRegisterInfo.td38 def R0 : GPR< 0, "$0">, DwarfRegNum<[0]>;
39 def R1 : GPR< 1, "$1">, DwarfRegNum<[1]>;
40 def R2 : GPR< 2, "$2">, DwarfRegNum<[2]>;
41 def R3 : GPR< 3, "$3">, DwarfRegNum<[3]>;
42 def R4 : GPR< 4, "$4">, DwarfRegNum<[4]>;
43 def R5 : GPR< 5, "$5">, DwarfRegNum<[5]>;
44 def R6 : GPR< 6, "$6">, DwarfRegNum<[6]>;
45 def R7 : GPR< 7, "$7">, DwarfRegNum<[7]>;
46 def R8 : GPR< 8, "$8">, DwarfRegNum<[8]>;
47 def R9 : GPR< 9, "$9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/MBlaze/
DMBlazeIntrinsics.td31 def int_mblaze_fsl_get : GCCBuiltin<"__builtin_mblaze_fsl_get">,
33 def int_mblaze_fsl_aget : GCCBuiltin<"__builtin_mblaze_fsl_aget">,
35 def int_mblaze_fsl_cget : GCCBuiltin<"__builtin_mblaze_fsl_cget">,
37 def int_mblaze_fsl_caget : GCCBuiltin<"__builtin_mblaze_fsl_caget">,
39 def int_mblaze_fsl_eget : GCCBuiltin<"__builtin_mblaze_fsl_eget">,
41 def int_mblaze_fsl_eaget : GCCBuiltin<"__builtin_mblaze_fsl_eaget">,
43 def int_mblaze_fsl_ecget : GCCBuiltin<"__builtin_mblaze_fsl_ecget">,
45 def int_mblaze_fsl_ecaget : GCCBuiltin<"__builtin_mblaze_fsl_ecaget">,
47 def int_mblaze_fsl_nget : GCCBuiltin<"__builtin_mblaze_fsl_nget">,
49 def int_mblaze_fsl_naget : GCCBuiltin<"__builtin_mblaze_fsl_naget">,
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DMBlazeRegisterInfo.td42 def R0 : MBlazeGPRReg< 0, "r0">, DwarfRegNum<[0]>;
43 def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>;
44 def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>;
45 def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>;
46 def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[4]>;
47 def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>;
48 def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>;
49 def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>;
50 def R8 : MBlazeGPRReg< 8, "r8">, DwarfRegNum<[8]>;
51 def R9 : MBlazeGPRReg< 9, "r9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/X86/
DX86RegisterInfo.td22 def sub_8bit : SubRegIndex;
23 def sub_8bit_hi : SubRegIndex;
24 def sub_16bit : SubRegIndex;
25 def sub_32bit : SubRegIndex;
27 def sub_ss : SubRegIndex;
28 def sub_sd : SubRegIndex;
29 def sub_xmm : SubRegIndex;
44 def AL : Register<"al">;
45 def DL : Register<"dl">;
46 def CL : Register<"cl">;
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/external/llvm/test/TableGen/
DSetTheory.td15 def a;
16 def b;
17 def c;
18 def d;
21 def add;
22 def S0a : Set<(add)>;
23 def S0b : Set<(add a)>;
24 def S0c : Set<(add a, b)>;
25 def S0d : Set<(add b, a)>;
26 def S0e : Set<(add a, a)>;
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