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/external/llvm/test/MC/ARM/
Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
[all …]
Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneon-reciprocal-encoding.s7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
11 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
12 vrecps.f32 d16, d16, d17
13 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
14 vrecps.f32 q8, q8, q9
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d16
[all …]
Dneont2-reciprocal-encoding.s9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
13 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f]
14 vrecps.f32 d16, d16, d17
15 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f]
16 vrecps.f32 q8, q8, q9
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d16
[all …]
Dsimple-fp-encoding.s6 @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
7 vadd.f32 s0, s1, s0
12 @ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
13 vsub.f32 s0, s1, s0
18 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
19 vdiv.f32 s0, s1, s0
24 @ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
25 vmul.f32 s0, s1, s0
30 @ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
31 vnmul.f32 s0, s1, s0
[all …]
Dneon-cmp-encoding.s16 @ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2]
17 vceq.f32 d16, d16, d17
24 @ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2]
25 vceq.f32 q8, q8, q9
39 @ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3]
40 vcge.f32 d16, d16, d17
53 @ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3]
54 vcge.f32 q8, q8, q9
55 @ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3]
56 vacge.f32 d16, d16, d17
[all …]
Dneon-minmax-encoding.s15 @ CHECK: vmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xf2]
16 vmin.f32 d16, d16, d17
29 @ CHECK: vmin.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x60,0xf2]
30 vmin.f32 q8, q8, q9
43 @ CHECK: vmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xf2]
44 vmax.f32 d16, d16, d17
57 @ CHECK: vmax.f32 q8, q8, q9 @ encoding: [0xe2,0x0f,0x40,0xf2]
58 vmax.f32 q8, q8, q9
/external/llvm/test/CodeGen/ARM/
Dfmacs.ll10 ; VFP2: vmla.f32
13 ; NEON: vmla.f32
16 ; A8: vmul.f32
17 ; A8: vadd.f32
42 ; VFP2: vmla.f32
45 ; NEON: vmla.f32
48 ; A8: vmul.f32
49 ; A8: vadd.f32
60 ; A8: vmul.f32
61 ; A8: vmul.f32
[all …]
Dneon_div.ll4 ;CHECK: vrecpe.f32
5 ;CHECK: vrecpe.f32
16 ;CHECK: vrecpe.f32
17 ;CHECK: vrecps.f32
18 ;CHECK: vrecpe.f32
19 ;CHECK: vrecps.f32
30 ;CHECK: vrecpe.f32
31 ;CHECK: vrecps.f32
40 ;CHECK: vrecpe.f32
41 ;CHECK: vrecps.f32
[all …]
Dfnegs.ll16 ; VFP2: vneg.f32 s{{.*}}, s{{.*}}
19 ; NFP1: vneg.f32 d{{.*}}, d{{.*}}
22 ; NFP0: vneg.f32 s{{.*}}, s{{.*}}
25 ; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}}
28 ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
40 ; VFP2: vneg.f32 s{{.*}}, s{{.*}}
43 ; NFP1: vneg.f32 d{{.*}}, d{{.*}}
46 ; NFP0: vneg.f32 s{{.*}}, s{{.*}}
49 ; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}}
52 ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}}
Dneon_minmax.ll5 ;CHECK: vmin.f32
13 ;CHECK-NOT: vmin.f32
21 ;CHECK: vmin.f32
29 ;CHECK: vmax.f32
37 ;CHECK: vmax.f32
45 ;CHECK-NOT: vmax.f32
53 ;CHECK: vmax.f32
61 ;CHECK: vmax.f32
69 ;CHECK: vmin.f32
77 ;CHECK: vmin.f32
Dfp_convert.ll8 ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
10 ; NEON: vcvt.s32.f32 d0, d0
19 ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
21 ; NEON: vcvt.u32.f32 d0, d0
30 ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
32 ; NEON: vcvt.f32.u32 d0, d0
41 ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
43 ; NEON: vcvt.f32.s32 d0, d0
Dvcvt.ll5 ;CHECK: vcvt.s32.f32
13 ;CHECK: vcvt.u32.f32
21 ;CHECK: vcvt.f32.s32
29 ;CHECK: vcvt.f32.u32
37 ;CHECK: vcvt.s32.f32
45 ;CHECK: vcvt.u32.f32
53 ;CHECK: vcvt.f32.s32
61 ;CHECK: vcvt.f32.u32
69 ;CHECK: vcvt.s32.f32
77 ;CHECK: vcvt.u32.f32
[all …]
Dvfcmp.ll8 ;CHECK: vceq.f32
20 ;CHECK: vcgt.f32
31 ;CHECK: vcge.f32
42 ;CHECK: vcgt.f32
54 ;CHECK: vcgt.f32
66 ;CHECK: vcge.f32
78 ;CHECK: vcge.f32
90 ;CHECK: vcgt.f32
91 ;CHECK-NEXT: vcgt.f32
104 ;CHECK: vcgt.f32
[all …]
Dfnmscs.ll9 ; VFP2: vnmla.f32
12 ; NEON: vnmla.f32
15 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
16 ; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
26 ; VFP2: vnmla.f32
29 ; NEON: vnmla.f32
32 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
33 ; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
Dfadds.ll13 ; VFP2: vadd.f32 s0, s1, s0
16 ; NFP1: vadd.f32 d0, d1, d0
18 ; NFP0: vadd.f32 s0, s1, s0
21 ; CORTEXA8: vadd.f32 d0, d1, d0
23 ; CORTEXA9: vadd.f32 s{{.}}, s{{.}}, s{{.}}
Dfdivs.ll13 ; VFP2: vdiv.f32 s0, s1, s0
16 ; NFP1: vdiv.f32 s0, s1, s0
18 ; NFP0: vdiv.f32 s0, s1, s0
21 ; CORTEXA8: vdiv.f32 s0, s1, s0
23 ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
Dfmuls.ll13 ; VFP2: vmul.f32 s0, s1, s0
16 ; NFP1: vmul.f32 d0, d1, d0
18 ; NFP0: vmul.f32 s0, s1, s0
21 ; CORTEXA8: vmul.f32 d0, d1, d0
23 ; CORTEXA9: vmul.f32 s{{.}}, s{{.}}, s{{.}}
Dfabss.ll17 ; VFP2: vabs.f32 s1, s1
20 ; NFP1: vabs.f32 d1, d1
22 ; NFP0: vabs.f32 s1, s1
25 ; CORTEXA8: vabs.f32 d1, d1
27 ; CORTEXA9: vabs.f32 s{{.}}, s{{.}}
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrFPU.td24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>;
29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>;
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
[all …]
/external/llvm/test/CodeGen/X86/
Dlimited-prec.ll11 %0 = call float @llvm.exp.f32(float %x) ; <float> [#uses=1]
15 declare float @llvm.exp.f32(float) nounwind readonly
20 %0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1]
24 declare float @llvm.exp2.f32(float) nounwind readonly
29 %0 = call float @llvm.pow.f32(float 1.000000e+01, float %x) ; <float> [#uses=1]
33 declare float @llvm.pow.f32(float, float) nounwind readonly
38 %0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1]
42 declare float @llvm.log.f32(float) nounwind readonly
47 %0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1]
51 declare float @llvm.log2.f32(float) nounwind readonly
[all …]
/external/qemu/target-arm/
Dhelper.h77 DEF_HELPER_3(vfp_adds, f32, f32, f32, env)
79 DEF_HELPER_3(vfp_subs, f32, f32, f32, env)
81 DEF_HELPER_3(vfp_muls, f32, f32, f32, env)
83 DEF_HELPER_3(vfp_divs, f32, f32, f32, env)
85 DEF_HELPER_1(vfp_negs, f32, f32)
87 DEF_HELPER_1(vfp_abss, f32, f32)
89 DEF_HELPER_2(vfp_sqrts, f32, f32, env)
91 DEF_HELPER_3(vfp_cmps, void, f32, f32, env)
93 DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
96 DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
[all …]
/external/llvm/test/CodeGen/PTX/
Dllvm-intrinsic.ll5 ; CHECK: sqrt.rn.f32 r{{[0-9]+}}, r{{[0-9]+}};
7 %y = call float @llvm.sqrt.f32(float %x)
21 ; CHECK: sin.approx.f32 r{{[0-9]+}}, r{{[0-9]+}};
23 %y = call float @llvm.sin.f32(float %x)
37 ; CHECK: cos.approx.f32 r{{[0-9]+}}, r{{[0-9]+}};
39 %y = call float @llvm.cos.f32(float %x)
51 declare float @llvm.sqrt.f32(float)
53 declare float @llvm.sin.f32(float)
55 declare float @llvm.cos.f32(float)
Daggregates.ll7 ; CHECK: ld.param.f32 r[[R0:[0-9]+]], [__param_1];
8 ; CHECK-NEXT: ld.param.f32 r[[R2:[0-9]+]], [__param_3];
9 ; CHECK-NEXT: ld.param.f32 r[[R1:[0-9]+]], [__param_2];
10 ; CHECK-NEXT: ld.param.f32 r[[R3:[0-9]+]], [__param_4];
11 ; CHECK-NEXT: add.rn.f32 r[[R0]], r[[R0]], r[[R2]];
12 ; CHECK-NEXT: add.rn.f32 r[[R1]], r[[R1]], r[[R3]];

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