/external/llvm/lib/Target/X86/InstPrinter/ |
D | X86InstComments.cpp | 37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() 49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments() 50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() 55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 58 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() 64 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments() 67 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments() [all …]
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D | X86ATTInstPrinter.cpp | 91 O << '%' << getRegisterName(Op.getReg()); in printOperand() 112 if (SegReg.getReg()) { in printMemReference() 119 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference() 126 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference() 128 if (BaseReg.getReg()) in printMemReference() 131 if (IndexReg.getReg()) { in printMemReference()
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D | X86IntelInstPrinter.cpp | 83 PrintRegName(O, getRegisterName(Op.getReg())); in printOperand() 101 if (SegReg.getReg()) { in printMemReference() 109 if (BaseReg.getReg()) { in printMemReference() 114 if (IndexReg.getReg()) { in printMemReference() 129 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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/external/llvm/lib/Target/ARM/InstPrinter/ |
D | ARMInstPrinter.cpp | 51 O << '\t' << getRegisterName(Dst.getReg()) in printInst() 52 << ", " << getRegisterName(MO1.getReg()); in printInst() 59 if (MO2.getReg()) { in printInst() 60 O << getRegisterName(MO2.getReg()); in printInst() 70 MI->getOperand(0).getReg() == ARM::SP) { in printInst() 82 MI->getOperand(0).getReg() == ARM::SP) { in printInst() 94 MI->getOperand(0).getReg() == ARM::SP) { in printInst() 104 MI->getOperand(0).getReg() == ARM::SP) { in printInst() 114 unsigned BaseReg = MI->getOperand(0).getReg(); in printInst() 116 if (MI->getOperand(i).getReg() == BaseReg) in printInst() [all …]
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/external/llvm/lib/CodeGen/ |
D | ProcessImplicitDefs.cpp | 54 ImpDefRegs.count(MI->getOperand(0).getReg())); in CanTurnIntoImplicitDef() 57 ImpDefRegs.count(MI->getOperand(0).getReg())); in CanTurnIntoImplicitDef() 67 if (MO1.getReg() != Reg) in isUndefCopy() 69 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg())) in isUndefCopy() 110 unsigned Reg = MI->getOperand(0).getReg(); in runOnMachineFunction() 123 if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) { in runOnMachineFunction() 125 LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg()); in runOnMachineFunction() 139 unsigned Reg = MO.getReg(); in runOnMachineFunction() 172 if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg) in runOnMachineFunction() 187 ImpDefRegs.erase(MO.getReg()); in runOnMachineFunction() [all …]
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D | TwoAddressInstructionPass.cpp | 192 unsigned MOReg = MO.getReg(); in Sink3AddrInstruction() 196 UseRegs.insert(MO.getReg()); in Sink3AddrInstruction() 205 DefReg = MO.getReg(); in Sink3AddrInstruction() 246 unsigned MOReg = MO.getReg(); in Sink3AddrInstruction() 286 if (MO.isReg() && MO.getReg() == Reg && in isTwoAddrUse() 390 DstReg = MI.getOperand(0).getReg(); in isCopyToReg() 391 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg() 393 DstReg = MI.getOperand(0).getReg(); in isCopyToReg() 394 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg() 451 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse() [all …]
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D | LowerSubregs.cpp | 99 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true)); in TransferImplicitDefs() 110 unsigned DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() 111 unsigned InsReg = MI->getOperand(2).getReg(); in LowerSubregToReg() 159 if (SrcMO.getReg() == DstMO.getReg()) { in LowerCopy() 177 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy() 180 TransferDeadFlag(MI, DstMO.getReg(), TRI); in LowerCopy()
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D | TargetInstrInfoImpl.cpp | 77 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() 78 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() 82 if (HasDef && MI->getOperand(0).getReg() == Reg1) { in commuteInstruction() 93 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0; in commuteInstruction() 148 MO.setReg(Pred[j].getReg()); in PredicateInstruction() 170 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize() 203 unsigned FoldReg = FoldOp.getReg(); in canFoldCopy() 204 unsigned LiveReg = LiveOp.getReg(); in canFoldCopy() 212 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg())) in canFoldCopy() 213 return RC->contains(LiveOp.getReg()) ? RC : 0; in canFoldCopy() [all …]
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D | OptimizePHIs.cpp | 88 unsigned DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() 100 unsigned SrcReg = MI->getOperand(i).getReg(); in IsSingleValuePHICycle() 109 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg())) in IsSingleValuePHICycle() 110 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); in IsSingleValuePHICycle() 131 unsigned DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() 168 MRI->replaceRegWith(MI->getOperand(0).getReg(), SingleValReg); in OptimizeBB()
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D | MachineLICM.cpp | 375 unsigned Reg = MO.getReg(); in ProcessMI() 477 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA() 479 if (PhysRegDefs[MO.getReg()]) { in HoistRegionPostRA() 507 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns() 508 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg())) in AddToLiveIns() 596 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg()); in isOperandKill() 623 unsigned Reg = MO.getReg(); in InitRegPressure() 656 unsigned Reg = MO.getReg(); in UpdateRegPressure() 714 unsigned Reg = MO.getReg(); in IsLoopInvariantInst() 774 unsigned Def = UseMI->getOperand(0).getReg(); in HasAnyPHIUse() [all …]
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D | ScheduleDAGEmit.cpp | 49 if (II->getReg()) { in EmitPhysRegCopy() 50 Reg = II->getReg(); in EmitPhysRegCopy() 58 assert(I->getReg() && "Unknown physical register!"); in EmitPhysRegCopy() 64 .addReg(I->getReg()); in EmitPhysRegCopy()
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D | MachineInstr.cpp | 64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); in AddRegOperandToRegInfo() 74 assert(getReg() == Contents.Reg.Next->getReg() && in AddRegOperandToRegInfo() 91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); in RemoveRegOperandFromRegInfo() 99 if (getReg() == Reg) return; // No change. in setReg() 196 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo() 240 OS << PrintReg(getReg(), TRI, getSubReg()); in print() 788 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || in isIdenticalTo() 789 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) in isIdenticalTo() 790 if (MO.getReg() != OMO.getReg()) in isIdenticalTo() 872 unsigned MOReg = MO.getReg(); in findRegisterUseOperandIdx() [all …]
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D | RegisterScavenging.cpp | 159 unsigned Reg = MO.getReg(); in forward() 186 unsigned Reg = MO.getReg(); in forward() 288 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) in findSurvivorReg() 290 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { in findSurvivorReg() 297 Candidates.reset(MO.getReg()); in findSurvivorReg() 298 for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++) in findSurvivorReg() 339 if (MO.isReg() && MO.getReg() != 0 && in scavengeRegister() 340 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) in scavengeRegister() 341 Candidates.reset(MO.getReg()); in scavengeRegister()
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D | MachineSSAUpdater.cpp | 94 unsigned SrcReg = I->getOperand(i).getReg(); in LookForIdenticalPHI() 102 return I->getOperand(0).getReg(); in LookForIdenticalPHI() 152 return NewDef->getOperand(0).getReg(); in GetValueInMiddleOfBlock() 205 return InsertedPHI->getOperand(0).getReg(); in GetValueInMiddleOfBlock() 262 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); } in getIncomingValue() 307 return NewDef->getOperand(0).getReg(); in GetUndefVal() 318 return PHI->getOperand(0).getReg(); in CreateEmptyPHI() 355 return PHI->getOperand(0).getReg(); in GetPHIValue()
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D | StrongPHIElimination.cpp | 226 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg) in findLastUse() 243 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() 249 unsigned SrcReg = SrcMO.getReg(); in runOnMachineFunction() 287 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() 291 unsigned SrcReg = BBI->getOperand(i).getReg(); in runOnMachineFunction() 308 unsigned SrcReg = PHI->getOperand(1).getReg(); in runOnMachineFunction() 317 unsigned DestReg = PHI->getOperand(0).getReg(); in runOnMachineFunction() 322 unsigned SrcReg = PHI->getOperand(i).getReg(); in runOnMachineFunction() 462 unsigned DestReg = PHI->getOperand(0).getReg(); in getPHIColor() 468 unsigned SrcColor = getRegColor(PHI->getOperand(i).getReg()); in getPHIColor() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86MCCodeEmitter.cpp | 48 return X86_MC::getX86RegNum(MO.getReg()); in GetX86RegNum() 62 unsigned SrcReg = MI.getOperand(OpNum).getReg(); in getVEXRegisterEncoding() 163 if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) || in Is32BitMemOperand() 164 (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg()))) in Is32BitMemOperand() 244 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() 249 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); in EmitMemModRMByte() 280 IndexReg.getReg() == 0 && in EmitMemModRMByte() 319 assert(IndexReg.getReg() != X86::ESP && in EmitMemModRMByte() 320 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in EmitMemModRMByte() 356 if (IndexReg.getReg()) in EmitMemModRMByte() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMMCCodeEmitter.cpp | 216 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue() 405 unsigned Reg = MO.getReg(); in getMachineOpValue() 436 Reg = getARMRegisterNumbering(MO.getReg()); in EncodeAddrModeOpValues() 517 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch() 617 unsigned Rn = getARMRegisterNumbering(MO1.getReg()); in getThumbAddrModeRegRegOpValue() 618 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); in getThumbAddrModeRegRegOpValue() 761 unsigned Rn = getARMRegisterNumbering(MO.getReg()); in getLdStSORegOpValue() 762 unsigned Rm = getARMRegisterNumbering(MO1.getReg()); in getLdStSORegOpValue() 792 unsigned Rn = getARMRegisterNumbering(MO.getReg()); in getAddrMode2OpValue() 808 bool isReg = MO.getReg() != 0; in getAddrMode2OffsetOpValue() [all …]
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D | MLxExpansionPass.cpp | 87 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() 97 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI() 103 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI() 115 unsigned Reg = MI->getOperand(0).getReg(); in getDefReg() 126 Reg = UseMI->getOperand(0).getReg(); in getDefReg() 209 unsigned DstReg = MI->getOperand(0).getReg(); in ExpandFPMLxInstruction() 211 unsigned AccReg = MI->getOperand(1).getReg(); in ExpandFPMLxInstruction() 212 unsigned Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() 213 unsigned Src2Reg = MI->getOperand(3).getReg(); in ExpandFPMLxInstruction() 219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction()
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D | ARMAsmPrinter.cpp | 168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); in getDebugValueLocation() 178 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) in EmitDwarfRegOp() 181 unsigned Reg = MLoc.getReg(); in EmitDwarfRegOp() 263 unsigned Reg = MO.getReg(); in printOperand() 354 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) in PrintAsmOperand() 373 unsigned Reg = MI->getOperand(OpNum).getReg(); in PrintAsmOperand() 394 unsigned RegBegin = MO.getReg(); in PrintAsmOperand() 408 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg()); in PrintAsmOperand() 447 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()); in PrintAsmMemoryOperand() 454 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]"; in PrintAsmMemoryOperand() [all …]
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D | Thumb2SizeReduction.cpp | 222 unsigned Reg = MO.getReg(); in canAddPseudoFlagDep() 232 unsigned Reg = MO.getReg(); in canAddPseudoFlagDep() 295 unsigned Reg = MO.getReg(); in VerifyLowRegs() 335 if (MI->getOperand(1).getReg() == ARM::SP) { in ReduceLoadStore() 369 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() 377 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore() 391 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() 405 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() 425 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore() 484 if (MI->getOperand(1).getReg() != ARM::SP) { in ReduceSpecial() [all …]
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/external/llvm/lib/Target/Alpha/ |
D | AlphaLLRP.cpp | 70 if (MI->getOperand(2).getReg() == Alpha::R30) { in runOnMachineFunction() 72 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&& in runOnMachineFunction() 83 && prev[1]->getOperand(2).getReg() == in runOnMachineFunction() 84 MI->getOperand(2).getReg() in runOnMachineFunction() 98 && prev[2]->getOperand(2).getReg() == in runOnMachineFunction() 99 MI->getOperand(2).getReg() in runOnMachineFunction()
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/external/llvm/lib/Target/Mips/ |
D | MipsExpandPseudo.cpp | 88 unsigned DstReg = I->getOperand(0).getReg(); in ExpandBuildPairF64() 89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in ExpandBuildPairF64() 103 unsigned DstReg = I->getOperand(0).getReg(); in ExpandExtractElementF64() 104 unsigned SrcReg = I->getOperand(1).getReg(); in ExpandExtractElementF64()
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/external/llvm/lib/CodeGen/AsmPrinter/ |
D | AsmPrinterDwarf.cpp | 217 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove() 218 if (Src.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove() 222 OutStreamer.EmitCFIDefCfa(RI->getDwarfRegNum(Src.getReg(), true), in EmitCFIFrameMove() 225 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove() 227 OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true)); in EmitCFIFrameMove() 230 OutStreamer.EmitCFIOffset(RI->getDwarfRegNum(Src.getReg(), true), in EmitCFIFrameMove()
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/external/llvm/lib/Target/MSP430/InstPrinter/ |
D | MSP430InstPrinter.cpp | 48 O << getRegisterName(Op.getReg()); in printOperand() 71 if (!Base.getReg()) in printSrcMemOperand() 82 if (Base.getReg()) in printSrcMemOperand() 83 O << '(' << getRegisterName(Base.getReg()) << ')'; in printSrcMemOperand()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZAsmPrinter.cpp | 128 assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && in printOperand() 130 unsigned Reg = MO.getReg(); in printOperand() 191 if (Base.getReg()) { in printRIAddrOperand() 208 if (Base.getReg()) { in printRRIAddrOperand() 211 if (Index.getReg()) { in printRRIAddrOperand() 217 assert(!Index.getReg() && "Should allocate base register first!"); in printRRIAddrOperand()
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