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/external/llvm/test/CodeGen/CellSPU/
Dicmp16.ll13 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-…
28 ; i16 integer comparisons:
29 define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
31 %A = icmp eq i16 %arg1, %arg2
32 %B = select i1 %A, i16 %val1, i16 %val2
33 ret i16 %B
36 define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
38 %A = icmp eq i16 %arg1, %arg2
42 define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
44 %A = icmp eq i16 %arg1, 511
[all …]
Dor_ops.ll7 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-…
21 define <8 x i16> @or_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
22 %A = or <8 x i16> %arg1, %arg2
23 ret <8 x i16> %A
26 define <8 x i16> @or_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
27 %A = or <8 x i16> %arg2, %arg1
28 ret <8 x i16> %A
51 define i16 @or_i16_1(i16 %arg1, i16 %arg2) {
52 %A = or i16 %arg2, %arg1
53 ret i16 %A
[all …]
Dand_ops.ll8 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-…
22 define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
23 %A = and <8 x i16> %arg1, %arg2
24 ret <8 x i16> %A
27 define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
28 %A = and <8 x i16> %arg2, %arg1
29 ret <8 x i16> %A
52 define i16 @and_i16_1(i16 %arg1, i16 %arg2) {
53 %A = and i16 %arg2, %arg1
54 ret i16 %A
[all …]
/external/llvm/test/CodeGen/MSP430/
Dmult-alt-generic-msp430.ll3 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
6 @mout0 = common global i16 0, align 2
7 @min1 = common global i16 0, align 2
8 @marray = common global [2 x i16] zeroinitializer, align 2
12 call void asm "foo $1,$0", "=*m,*m"(i16* @mout0, i16* @min1) nounwind
18 %out0 = alloca i16, align 2
19 %index = alloca i16, align 2
20 store i16 0, i16* %out0, align 2
21 store i16 1, i16* %index, align 2
32 %out0 = alloca i16, align 2
[all …]
Dpostinc.ll2 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
5 define zeroext i16 @add(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
7 %cmp8 = icmp eq i16 %n, 0 ; <i1> [#uses=1]
11 %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
12 %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
13 %arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
16 %tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
17 %add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2]
18 %inc = add i16 %i.010, 1 ; <i16> [#uses=2]
19 %exitcond = icmp eq i16 %inc, %n ; <i1> [#uses=1]
[all …]
Dsetcc.ll2 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
5 define i16 @sccweqand(i16 %a, i16 %b) nounwind {
6 %t1 = and i16 %a, %b
7 %t2 = icmp eq i16 %t1, 0
8 %t3 = zext i1 %t2 to i16
9 ret i16 %t3
17 define i16 @sccwneand(i16 %a, i16 %b) nounwind {
18 %t1 = and i16 %a, %b
19 %t2 = icmp ne i16 %t1, 0
20 %t3 = zext i1 %t2 to i16
[all …]
DAddrMode-bis-rx.ll2 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
5 define i16 @am1(i16 %x, i16* %a) nounwind {
6 %1 = load i16* %a
7 %2 = or i16 %1,%x
8 ret i16 %2
13 @foo = external global i16
15 define i16 @am2(i16 %x) nounwind {
16 %1 = load i16* @foo
17 %2 = or i16 %1,%x
18 ret i16 %2
[all …]
DAddrMode-bis-xr.ll2 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
5 define void @am1(i16* %a, i16 %x) nounwind {
6 %1 = load i16* %a
7 %2 = or i16 %x, %1
8 store i16 %2, i16* %a
14 @foo = external global i16
16 define void @am2(i16 %x) nounwind {
17 %1 = load i16* @foo
18 %2 = or i16 %x, %1
19 store i16 %2, i16* @foo
[all …]
DInst16mm.ll2 target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
4 @foo = common global i16 0, align 2
5 @bar = common global i16 0, align 2
10 %1 = load i16* @bar
11 store i16 %1, i16* @foo
18 %1 = load i16* @bar
19 %2 = load i16* @foo
20 %3 = add i16 %2, %1
21 store i16 %3, i16* @foo
28 %1 = load i16* @bar
[all …]
/external/llvm/test/CodeGen/X86/
Dbyval4.ll27 %struct.s = type { i16, i16, i16, i16, i16, i16, i16, i16,
28 i16, i16, i16, i16, i16, i16, i16, i16,
29 i16, i16, i16, i16, i16, i16, i16, i16,
30 i16, i16, i16, i16, i16, i16, i16, i16,
31 i16, i16, i16, i16, i16, i16, i16, i16,
32 i16, i16, i16, i16, i16, i16, i16, i16,
33 i16, i16, i16, i16, i16, i16, i16, i16,
34 i16, i16, i16, i16, i16, i16, i16, i16,
35 i16 }
38 define void @g(i16 signext %a1, i16 signext %a2, i16 signext %a3,
[all …]
Dpic-load-remat.ll8 …3 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
9 …3 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
10 …<8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, …
11 …%tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <…
12 …ll <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x i32> < i32 4, i32 …
13 …i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
15 %tmp4689 = add <8 x i16> %tmp4679, %tmp4658 ; <<8 x i16>> [#uses=1]
16 …4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializer )…
17 %tmp4708 = bitcast <8 x i16> %tmp4700 to <2 x i64> ; <<2 x i64>> [#uses=1]
[all …]
Drot16.ll3 define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
7 %0 = shl i16 %x, %z
8 %1 = sub i16 16, %z
9 %2 = lshr i16 %x, %1
10 %3 = or i16 %2, %0
11 ret i16 %3
14 define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
18 %0 = shl i16 %y, %z
19 %1 = sub i16 16, %z
20 %2 = lshr i16 %x, %1
[all …]
Dx86-shifts.ll62 define <8 x i16> @shl8(<8 x i16> %A) nounwind {
67 %B = shl <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
68 %C = shl <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
69 %K = xor <8 x i16> %B, %C
70 ret <8 x i16> %K
73 define <8 x i16> @shr8(<8 x i16> %A) nounwind {
78 %B = lshr <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
79 %C = lshr <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
80 %K = xor <8 x i16> %B, %C
81 ret <8 x i16> %K
[all …]
Dvec_set.ll3 define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16…
4 … %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]
5 %tmp2 = insertelement <8 x i16> %tmp, i16 %a1, i32 1 ; <<8 x i16>> [#uses=1]
6 %tmp4 = insertelement <8 x i16> %tmp2, i16 %a2, i32 2 ; <<8 x i16>> [#uses=1]
7 %tmp6 = insertelement <8 x i16> %tmp4, i16 %a3, i32 3 ; <<8 x i16>> [#uses=1]
8 %tmp8 = insertelement <8 x i16> %tmp6, i16 %a4, i32 4 ; <<8 x i16>> [#uses=1]
9 %tmp10 = insertelement <8 x i16> %tmp8, i16 %a5, i32 5 ; <<8 x i16>> [#uses=1]
10 %tmp12 = insertelement <8 x i16> %tmp10, i16 %a6, i32 6 ; <<8 x i16>> [#uses=1]
11 %tmp14 = insertelement <8 x i16> %tmp12, i16 %a7, i32 7 ; <<8 x i16>> [#uses=1]
12 store <8 x i16> %tmp14, <8 x i16>* %b
Dwiden_arith-4.ll7 define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind {
9 %dst.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
10 %src.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
12 %v = alloca <5 x i16>, align 16 ; <<5 x i16>*> [#uses=1]
14 store <5 x i16>* %dst, <5 x i16>** %dst.addr
15 store <5 x i16>* %src, <5 x i16>** %src.addr
17 store <5 x i16> < i16 1, i16 1, i16 1, i16 0, i16 0 >, <5 x i16>* %v
29 %tmp3 = load <5 x i16>** %dst.addr ; <<5 x i16>*> [#uses=1]
30 %arrayidx = getelementptr <5 x i16>* %tmp3, i32 %tmp2 ; <<5 x i16>*> [#uses=1]
32 %tmp5 = load <5 x i16>** %src.addr ; <<5 x i16>*> [#uses=1]
[all …]
D2008-04-16-ReMatBug.ll3 …i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i…
4 %struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
5 %struct.GENV_t = type { i32, i8*, i16, i8*, i8*, i32, i32, i32, i32, %struct.DBC_t*, i16 }
9 …i16 @SQLDriversW(i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* …
14 ret i16 0
18 %tmp46 = getelementptr %struct.GENV_t* %tmp12, i32 0, i32 10 ; <i16*> [#uses=1]
19 store i16 0, i16* %tmp46, align 4
24 %tmp95180 = shl i16 %cbDrvAttrMax, 2 ; <i16> [#uses=1]
25 %tmp100178 = shl i16 %cbDrvDescMax, 2 ; <i16> [#uses=1]
26 …i16 @SQLDrivers_Internal( i8* %henv, i16 zeroext %fDir, i8* null, i16 signext %tmp100178, i16* %…
[all …]
/external/llvm/test/Analysis/ScalarEvolution/
D2008-08-04-LongAddRec.ll10 add i16 %x17.0, 1 ; <i16>:0 [#uses=2]
11 add i16 %0, %x16.0 ; <i16>:1 [#uses=2]
12 add i16 %1, %x15.0 ; <i16>:2 [#uses=2]
13 add i16 %2, %x14.0 ; <i16>:3 [#uses=2]
14 add i16 %3, %x13.0 ; <i16>:4 [#uses=2]
15 add i16 %4, %x12.0 ; <i16>:5 [#uses=2]
16 add i16 %5, %x11.0 ; <i16>:6 [#uses=2]
17 add i16 %6, %x10.0 ; <i16>:7 [#uses=2]
18 add i16 %7, %x9.0 ; <i16>:8 [#uses=2]
19 add i16 %8, %x8.0 ; <i16>:9 [#uses=2]
[all …]
/external/llvm/test/CodeGen/Blackfin/
Dbasic-i16.ll3 define i16 @add(i16 %A, i16 %B) {
4 %R = add i16 %A, %B ; <i16> [#uses=1]
5 ret i16 %R
8 define i16 @sub(i16 %A, i16 %B) {
9 %R = sub i16 %A, %B ; <i16> [#uses=1]
10 ret i16 %R
13 define i16 @mul(i16 %A, i16 %B) {
14 %R = mul i16 %A, %B ; <i16> [#uses=1]
15 ret i16 %R
18 define i16 @sdiv(i16 %A, i16 %B) {
[all …]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-strh.ll3 define i16 @f1(i16 %a, i16* %v) {
6 store i16 %a, i16* %v
7 ret i16 %a
10 define i16 @f2(i16 %a, i16* %v) {
13 %tmp2 = getelementptr i16* %v, i32 2046
14 store i16 %a, i16* %tmp2
15 ret i16 %a
18 define i16 @f2a(i16 %a, i16* %v) {
21 %tmp2 = getelementptr i16* %v, i32 -64
22 store i16 %a, i16* %tmp2
[all …]
/external/llvm/test/Transforms/DeadArgElim/
Dmultdeadretval.ll2 ; are unused. All unused values are typed i16, so we can easily check. We also
5 ; RUN: opt < %s -deadargelim -instcombine -dce -S | not grep i16
7 define internal {i16, i32} @test(i16 %DEADARG) {
8 %A = insertvalue {i16,i32} undef, i16 1, 0
9 %B = insertvalue {i16,i32} %A, i32 1001, 1
10 ret {i16,i32} %B
13 define internal {i32, i16} @test2() {
14 %DEAD = call i16 @test4()
15 %A = insertvalue {i32,i16} undef, i32 1, 0
16 %B = insertvalue {i32,i16} %A, i16 %DEAD, 1
[all …]
/external/llvm/test/CodeGen/PowerPC/
D2007-06-28-BCCISelBug.ll3 %struct.XATest = type { float, i16, i8, i8 }
5 %struct.XBlendMode = type { i16, i16, i16, i16, %struct.GIC4, i16, i16, i8, i8, i8, i8 }
8 %struct.XCBuffer = type { i16, i16, [8 x i16] }
10 %struct.XConvolution = type { %struct.GIC4, %struct.XICSS, i16, i16, float*, i32, i32 }
11 %struct.XDepthTest = type { i16, i16, i8, i8, i8, i8, double, double }
13 %struct.XFogMode = type { %struct.GIC4, float, float, float, float, float, i16, i16, i16, i8, i8 }
15 %struct.XHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }
16 %struct.XHistogram = type { %struct.XFramebufferAttachment*, i32, i16, i8, i8 }
20 …e { %struct.GIC4, [8 x %struct.XLight], [2 x %struct.XMaterial], i32, i16, i16, i16, i8, i8, i8, i…
22 %struct.XLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 }
[all …]
DAtomics-64.ll9 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v…
13 @ss = common global i16 0 ; <i16*> [#uses=15]
14 @us = common global i16 0 ; <i16*> [#uses=15]
26 bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
27 call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0]
28 bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
29 call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0]
40 bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
41 call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0]
42 bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
[all …]
DAtomics-32.ll3 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v…
7 @ss = common global i16 0 ; <i16*> [#uses=15]
8 @us = common global i16 0 ; <i16*> [#uses=15]
20 bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
21 call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0]
22 bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
23 call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0]
34 bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
35 call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0]
36 bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
[all …]
/external/llvm/test/CodeGen/ARM/
Dvqshrn.ll3 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
6 %tmp1 = load <8 x i16>* %A
7 …@llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
11 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
15 …%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -1…
16 ret <4 x i16> %tmp2
27 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
30 %tmp1 = load <8 x i16>* %A
31 …@llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8,…
35 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
[all …]
/external/llvm/test/CodeGen/SystemZ/
D05-MemLoadsStores16.ll6 target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:12…
9 define void @foo1(i16* nocapture %foo, i16* nocapture %bar) nounwind {
11 %tmp1 = load i16* %foo ; <i16> [#uses=1]
12 store i16 %tmp1, i16* %bar
16 define void @foo2(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
18 %add.ptr = getelementptr i16* %foo, i64 1 ; <i16*> [#uses=1]
19 %tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
21 %add.ptr5 = getelementptr i16* %bar, i64 %add.ptr3.sum ; <i16*> [#uses=1]
22 store i16 %tmp1, i16* %add.ptr5
26 define void @foo3(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
[all …]

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