1; RUN: llc < %s -march=cellspu > %t1.s 2; RUN: grep and %t1.s | count 234 3; RUN: grep andc %t1.s | count 85 4; RUN: grep andi %t1.s | count 37 5; RUN: grep andhi %t1.s | count 30 6; RUN: grep andbi %t1.s | count 4 7 8target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" 9target triple = "spu" 10 11; AND instruction generation: 12define <4 x i32> @and_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) { 13 %A = and <4 x i32> %arg1, %arg2 14 ret <4 x i32> %A 15} 16 17define <4 x i32> @and_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) { 18 %A = and <4 x i32> %arg2, %arg1 19 ret <4 x i32> %A 20} 21 22define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) { 23 %A = and <8 x i16> %arg1, %arg2 24 ret <8 x i16> %A 25} 26 27define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) { 28 %A = and <8 x i16> %arg2, %arg1 29 ret <8 x i16> %A 30} 31 32define <16 x i8> @and_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) { 33 %A = and <16 x i8> %arg2, %arg1 34 ret <16 x i8> %A 35} 36 37define <16 x i8> @and_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) { 38 %A = and <16 x i8> %arg1, %arg2 39 ret <16 x i8> %A 40} 41 42define i32 @and_i32_1(i32 %arg1, i32 %arg2) { 43 %A = and i32 %arg2, %arg1 44 ret i32 %A 45} 46 47define i32 @and_i32_2(i32 %arg1, i32 %arg2) { 48 %A = and i32 %arg1, %arg2 49 ret i32 %A 50} 51 52define i16 @and_i16_1(i16 %arg1, i16 %arg2) { 53 %A = and i16 %arg2, %arg1 54 ret i16 %A 55} 56 57define i16 @and_i16_2(i16 %arg1, i16 %arg2) { 58 %A = and i16 %arg1, %arg2 59 ret i16 %A 60} 61 62define i8 @and_i8_1(i8 %arg1, i8 %arg2) { 63 %A = and i8 %arg2, %arg1 64 ret i8 %A 65} 66 67define i8 @and_i8_2(i8 %arg1, i8 %arg2) { 68 %A = and i8 %arg1, %arg2 69 ret i8 %A 70} 71 72; ANDC instruction generation: 73define <4 x i32> @andc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) { 74 %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 > 75 %B = and <4 x i32> %arg1, %A 76 ret <4 x i32> %B 77} 78 79define <4 x i32> @andc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) { 80 %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 > 81 %B = and <4 x i32> %arg2, %A 82 ret <4 x i32> %B 83} 84 85define <4 x i32> @andc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) { 86 %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 > 87 %B = and <4 x i32> %A, %arg2 88 ret <4 x i32> %B 89} 90 91define <8 x i16> @andc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) { 92 %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1, 93 i16 -1, i16 -1, i16 -1, i16 -1 > 94 %B = and <8 x i16> %arg1, %A 95 ret <8 x i16> %B 96} 97 98define <8 x i16> @andc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) { 99 %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1, 100 i16 -1, i16 -1, i16 -1, i16 -1 > 101 %B = and <8 x i16> %arg2, %A 102 ret <8 x i16> %B 103} 104 105define <16 x i8> @andc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) { 106 %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 107 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 108 i8 -1, i8 -1, i8 -1, i8 -1 > 109 %B = and <16 x i8> %arg2, %A 110 ret <16 x i8> %B 111} 112 113define <16 x i8> @andc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) { 114 %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 115 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 116 i8 -1, i8 -1, i8 -1, i8 -1 > 117 %B = and <16 x i8> %arg1, %A 118 ret <16 x i8> %B 119} 120 121define <16 x i8> @andc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) { 122 %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 123 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, 124 i8 -1, i8 -1, i8 -1, i8 -1 > 125 %B = and <16 x i8> %A, %arg1 126 ret <16 x i8> %B 127} 128 129define i32 @andc_i32_1(i32 %arg1, i32 %arg2) { 130 %A = xor i32 %arg2, -1 131 %B = and i32 %A, %arg1 132 ret i32 %B 133} 134 135define i32 @andc_i32_2(i32 %arg1, i32 %arg2) { 136 %A = xor i32 %arg1, -1 137 %B = and i32 %A, %arg2 138 ret i32 %B 139} 140 141define i32 @andc_i32_3(i32 %arg1, i32 %arg2) { 142 %A = xor i32 %arg2, -1 143 %B = and i32 %arg1, %A 144 ret i32 %B 145} 146 147define i16 @andc_i16_1(i16 %arg1, i16 %arg2) { 148 %A = xor i16 %arg2, -1 149 %B = and i16 %A, %arg1 150 ret i16 %B 151} 152 153define i16 @andc_i16_2(i16 %arg1, i16 %arg2) { 154 %A = xor i16 %arg1, -1 155 %B = and i16 %A, %arg2 156 ret i16 %B 157} 158 159define i16 @andc_i16_3(i16 %arg1, i16 %arg2) { 160 %A = xor i16 %arg2, -1 161 %B = and i16 %arg1, %A 162 ret i16 %B 163} 164 165define i8 @andc_i8_1(i8 %arg1, i8 %arg2) { 166 %A = xor i8 %arg2, -1 167 %B = and i8 %A, %arg1 168 ret i8 %B 169} 170 171define i8 @andc_i8_2(i8 %arg1, i8 %arg2) { 172 %A = xor i8 %arg1, -1 173 %B = and i8 %A, %arg2 174 ret i8 %B 175} 176 177define i8 @andc_i8_3(i8 %arg1, i8 %arg2) { 178 %A = xor i8 %arg2, -1 179 %B = and i8 %arg1, %A 180 ret i8 %B 181} 182 183; ANDI instruction generation (i32 data type): 184define <4 x i32> @andi_v4i32_1(<4 x i32> %in) { 185 %tmp2 = and <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 > 186 ret <4 x i32> %tmp2 187} 188 189define <4 x i32> @andi_v4i32_2(<4 x i32> %in) { 190 %tmp2 = and <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 > 191 ret <4 x i32> %tmp2 192} 193 194define <4 x i32> @andi_v4i32_3(<4 x i32> %in) { 195 %tmp2 = and <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 > 196 ret <4 x i32> %tmp2 197} 198 199define <4 x i32> @andi_v4i32_4(<4 x i32> %in) { 200 %tmp2 = and <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 > 201 ret <4 x i32> %tmp2 202} 203 204define zeroext i32 @andi_u32(i32 zeroext %in) { 205 %tmp37 = and i32 %in, 37 206 ret i32 %tmp37 207} 208 209define signext i32 @andi_i32(i32 signext %in) { 210 %tmp38 = and i32 %in, 37 211 ret i32 %tmp38 212} 213 214define i32 @andi_i32_1(i32 %in) { 215 %tmp37 = and i32 %in, 37 216 ret i32 %tmp37 217} 218 219; ANDHI instruction generation (i16 data type): 220define <8 x i16> @andhi_v8i16_1(<8 x i16> %in) { 221 %tmp2 = and <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511, 222 i16 511, i16 511, i16 511, i16 511 > 223 ret <8 x i16> %tmp2 224} 225 226define <8 x i16> @andhi_v8i16_2(<8 x i16> %in) { 227 %tmp2 = and <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510, 228 i16 510, i16 510, i16 510, i16 510 > 229 ret <8 x i16> %tmp2 230} 231 232define <8 x i16> @andhi_v8i16_3(<8 x i16> %in) { 233 %tmp2 = and <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, 234 i16 -1, i16 -1, i16 -1 > 235 ret <8 x i16> %tmp2 236} 237 238define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) { 239 %tmp2 = and <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512, 240 i16 -512, i16 -512, i16 -512, i16 -512 > 241 ret <8 x i16> %tmp2 242} 243 244define zeroext i16 @andhi_u16(i16 zeroext %in) { 245 %tmp37 = and i16 %in, 37 ; <i16> [#uses=1] 246 ret i16 %tmp37 247} 248 249define signext i16 @andhi_i16(i16 signext %in) { 250 %tmp38 = and i16 %in, 37 ; <i16> [#uses=1] 251 ret i16 %tmp38 252} 253 254; i8 data type (s/b ANDBI if 8-bit registers were supported): 255define <16 x i8> @and_v16i8(<16 x i8> %in) { 256 ; ANDBI generated for vector types 257 %tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, 258 i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, 259 i8 42, i8 42, i8 42, i8 42 > 260 ret <16 x i8> %tmp2 261} 262 263define zeroext i8 @and_u8(i8 zeroext %in) { 264 ; ANDBI generated: 265 %tmp37 = and i8 %in, 37 266 ret i8 %tmp37 267} 268 269define signext i8 @and_sext8(i8 signext %in) { 270 ; ANDBI generated 271 %tmp38 = and i8 %in, 37 272 ret i8 %tmp38 273} 274 275define i8 @and_i8(i8 %in) { 276 ; ANDBI generated 277 %tmp38 = and i8 %in, 205 278 ret i8 %tmp38 279} 280