1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 **************************************************************************** 11 ****************************************************************************/ 12 #ifndef __ASM_SH_HD64461 13 #define __ASM_SH_HD64461 14 15 #define HD64461_PCC_WINDOW 0x01000000 16 17 #define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 18 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) 19 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) 20 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) 21 22 #define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 23 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) 24 #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) 25 26 #define HD64461_STBCR CONFIG_HD64461_IOBASE 27 #define HD64461_STBCR_CKIO_STBY 0x2000 28 #define HD64461_STBCR_SAFECKE_IST 0x1000 29 #define HD64461_STBCR_SLCKE_IST 0x0800 30 #define HD64461_STBCR_SAFECKE_OST 0x0400 31 #define HD64461_STBCR_SLCKE_OST 0x0200 32 #define HD64461_STBCR_SMIAST 0x0100 33 #define HD64461_STBCR_SLCDST 0x0080 34 #define HD64461_STBCR_SPC0ST 0x0040 35 #define HD64461_STBCR_SPC1ST 0x0020 36 #define HD64461_STBCR_SAFEST 0x0010 37 #define HD64461_STBCR_STM0ST 0x0008 38 #define HD64461_STBCR_STM1ST 0x0004 39 #define HD64461_STBCR_SIRST 0x0002 40 #define HD64461_STBCR_SURTST 0x0001 41 42 #define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 43 44 #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 45 46 #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 47 48 #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 49 50 #define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 51 52 #define HD64461_LCDCCR_STBACK 0x0400 53 #define HD64461_LCDCCR_STREQ 0x0100 54 #define HD64461_LCDCCR_MOFF 0x0080 55 #define HD64461_LCDCCR_REFSEL 0x0040 56 #define HD64461_LCDCCR_EPON 0x0020 57 #define HD64461_LCDCCR_SPON 0x0010 58 59 #define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 60 #define HD64461_LDR1_DON 0x01 61 #define HD64461_LDR1_DINV 0x80 62 63 #define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 64 #define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) 65 #define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) 66 #define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) 67 #define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) 68 #define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) 69 70 #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 71 72 #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) 73 #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) 74 #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) 75 #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) 76 77 #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) 78 #define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) 79 #define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) 80 81 #define HD64461_GRCFGR_ACCSTATUS 0x10 82 #define HD64461_GRCFGR_ACCRESET 0x08 83 #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 84 #define HD64461_GRCFGR_ACCSTART_LINE 0x04 85 #define HD64461_GRCFGR_COLORDEPTH16 0x01 86 #define HD64461_GRCFGR_COLORDEPTH8 0x01 87 88 #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) 89 #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) 90 #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) 91 #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) 92 #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) 93 #define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) 94 #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) 95 96 #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) 97 #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) 98 #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) 99 #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) 100 #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) 101 #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) 102 #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) 103 #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) 104 #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) 105 #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) 106 #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) 107 #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) 108 109 #define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) 110 #define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) 111 #define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) 112 #define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) 113 #define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) 114 115 #define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) 116 #define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) 117 #define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) 118 #define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) 119 #define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) 120 121 #define HD64461_PCCISR_READY 0x80 122 #define HD64461_PCCISR_MWP 0x40 123 #define HD64461_PCCISR_VS2 0x20 124 #define HD64461_PCCISR_VS1 0x10 125 #define HD64461_PCCISR_CD2 0x08 126 #define HD64461_PCCISR_CD1 0x04 127 #define HD64461_PCCISR_BVD2 0x02 128 #define HD64461_PCCISR_BVD1 0x01 129 130 #define HD64461_PCCISR_PCD_MASK 0x0c 131 #define HD64461_PCCISR_BVD_MASK 0x03 132 #define HD64461_PCCISR_BVD_BATGOOD 0x03 133 #define HD64461_PCCISR_BVD_BATWARN 0x01 134 #define HD64461_PCCISR_BVD_BATDEAD1 0x02 135 #define HD64461_PCCISR_BVD_BATDEAD2 0x00 136 137 #define HD64461_PCCGCR_DRVE 0x80 138 #define HD64461_PCCGCR_PCCR 0x40 139 #define HD64461_PCCGCR_PCCT 0x20 140 #define HD64461_PCCGCR_VCC0 0x10 141 #define HD64461_PCCGCR_PMMOD 0x08 142 #define HD64461_PCCGCR_PA25 0x04 143 #define HD64461_PCCGCR_PA24 0x02 144 #define HD64461_PCCGCR_REG 0x01 145 146 #define HD64461_PCCCSCR_SCDI 0x80 147 #define HD64461_PCCCSCR_SRV1 0x40 148 #define HD64461_PCCCSCR_IREQ 0x20 149 #define HD64461_PCCCSCR_SC 0x10 150 #define HD64461_PCCCSCR_CDC 0x08 151 #define HD64461_PCCCSCR_RC 0x04 152 #define HD64461_PCCCSCR_BW 0x02 153 #define HD64461_PCCCSCR_BD 0x01 154 155 #define HD64461_PCCCSCIER_CRE 0x80 156 #define HD64461_PCCCSCIER_IREQE_MASK 0x60 157 #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 158 #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 159 #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 160 #define HD64461_PCCCSCIER_IREQE_RISING 0x60 161 162 #define HD64461_PCCCSCIER_SCE 0x10 163 #define HD64461_PCCCSCIER_CDE 0x08 164 #define HD64461_PCCCSCIER_RE 0x04 165 #define HD64461_PCCCSCIER_BWE 0x02 166 #define HD64461_PCCCSCIER_BDE 0x01 167 168 #define HD64461_PCCSCR_VCC1 0x02 169 #define HD64461_PCCSCR_SWP 0x01 170 171 #define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 172 173 #define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 174 175 #define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 176 177 #define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) 178 #define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) 179 #define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) 180 #define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) 181 182 #define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) 183 #define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) 184 #define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) 185 #define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) 186 187 #define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) 188 #define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) 189 #define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) 190 #define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) 191 192 #define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) 193 #define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) 194 #define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) 195 #define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) 196 197 #define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 198 #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 199 200 #define HD64461_IRQBASE OFFCHIP_IRQ_BASE 201 #define OFFCHIP_IRQ_BASE 64 202 #define HD64461_IRQ_NUM 16 203 204 #define HD64461_IRQ_UART (HD64461_IRQBASE+5) 205 #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) 206 #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) 207 #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) 208 #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) 209 #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) 210 #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) 211 #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) 212 213 #define __IO_PREFIX hd64461 214 #include <asm/io_generic.h> 215 216 #endif 217