1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __ASM_ARCH_MSM7200_IRQS_H 30 31 /* MSM7200 ARM11 Interrupt Numbers */ 32 /* See 80-VE113-1 A, pp219-221 */ 33 34 #define INT_A9_M2A_0 0 35 #define INT_A9_M2A_1 1 36 #define INT_A9_M2A_2 2 37 #define INT_A9_M2A_3 3 38 #define INT_A9_M2A_4 4 39 #define INT_A9_M2A_5 5 40 #define INT_A9_M2A_6 6 41 #define INT_GP_TIMER_EXP 7 42 #define INT_DEBUG_TIMER_EXP 8 43 #define INT_UART1 9 44 #define INT_UART2 10 45 #define INT_UART3 11 46 #define INT_UART1_RX 12 47 #define INT_UART2_RX 13 48 #define INT_UART3_RX 14 49 #define INT_USB_OTG 15 50 #define INT_MDDI_PRI 16 51 #define INT_MDDI_EXT 17 52 #define INT_MDDI_CLIENT 18 53 #define INT_MDP 19 54 #define INT_GRAPHICS 20 55 #define INT_ADM_AARM 21 56 #define INT_ADSP_A11 22 57 #define INT_ADSP_A9_A11 23 58 #define INT_SDC1_0 24 59 #define INT_SDC1_1 25 60 #define INT_SDC2_0 26 61 #define INT_SDC2_1 27 62 #define INT_KEYSENSE 28 63 #define INT_TCHSCRN_SSBI 29 64 #define INT_TCHSCRN1 30 65 #define INT_TCHSCRN2 31 66 67 #define INT_GPIO_GROUP1 (32 + 0) 68 #define INT_GPIO_GROUP2 (32 + 1) 69 #define INT_PWB_I2C (32 + 2) 70 #define INT_NAND_WR_ER_DONE (32 + 3) 71 #define INT_NAND_OP_DONE (32 + 4) 72 #define INT_SOFTRESET (32 + 5) 73 #define INT_PBUS_ARM11 (32 + 6) 74 #define INT_AXI_MPU_SMI (32 + 7) 75 #define INT_AXI_MPU_EBI1 (32 + 8) 76 #define INT_AD_HSSD (32 + 9) 77 #define INT_ARM11_PM (32 + 10) 78 #define INT_ARM11_DMA (32 + 11) 79 #define INT_TSIF_IRQ (32 + 12) 80 #define INT_UART1DM_IRQ (32 + 13) 81 #define INT_UART1DM_RX (32 + 14) 82 #define INT_SPARE0 (32 + 15) 83 84 #define MSM_IRQ_BIT(irq) (1 << ((irq) & 31)) 85 86 #define NR_IRQS 48 87 88 #endif 89