1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Mips.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Target/TargetRegistry.h"
18 using namespace llvm;
19
LLVMInitializeMipsTarget()20 extern "C" void LLVMInitializeMipsTarget() {
21 // Register the target.
22 RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
23 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
24 }
25
26 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
27 // The stack is always 8 byte aligned
28 // On function prologue, the stack is created by decrementing
29 // its pointer. Once decremented, all references are done with positive
30 // offset from the stack/frame pointer, using StackGrowsUp enables
31 // an easier handling.
32 // Using CodeModel::Large enables different CALL behavior.
33 MipsTargetMachine::
MipsTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,Reloc::Model RM,bool isLittle=false)34 MipsTargetMachine(const Target &T, StringRef TT,
35 StringRef CPU, StringRef FS, Reloc::Model RM,
36 bool isLittle=false):
37 LLVMTargetMachine(T, TT, CPU, FS, RM),
38 Subtarget(TT, CPU, FS, isLittle),
39 DataLayout(isLittle ?
40 std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
41 std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
42 InstrInfo(*this),
43 FrameLowering(Subtarget),
44 TLInfo(*this), TSInfo(*this) {
45 }
46
47 MipselTargetMachine::
MipselTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,Reloc::Model RM)48 MipselTargetMachine(const Target &T, StringRef TT,
49 StringRef CPU, StringRef FS, Reloc::Model RM) :
50 MipsTargetMachine(T, TT, CPU, FS, RM, true) {}
51
52 // Install an instruction selector pass using
53 // the ISelDag to gen Mips code.
54 bool MipsTargetMachine::
addInstSelector(PassManagerBase & PM,CodeGenOpt::Level OptLevel)55 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
56 {
57 PM.add(createMipsISelDag(*this));
58 return false;
59 }
60
61 // Implemented by targets that want to run passes immediately before
62 // machine code is emitted. return true if -print-machineinstrs should
63 // print out the code after the passes.
64 bool MipsTargetMachine::
addPreEmitPass(PassManagerBase & PM,CodeGenOpt::Level OptLevel)65 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
66 {
67 PM.add(createMipsDelaySlotFillerPass(*this));
68 return true;
69 }
70
71 bool MipsTargetMachine::
addPreRegAlloc(PassManagerBase & PM,CodeGenOpt::Level OptLevel)72 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
73 PM.add(createMipsEmitGPRestorePass(*this));
74 return true;
75 }
76
77 bool MipsTargetMachine::
addPostRegAlloc(PassManagerBase & PM,CodeGenOpt::Level OptLevel)78 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
79 PM.add(createMipsExpandPseudoPass(*this));
80 return true;
81 }
82