1########################################################### 2## Commands for running tblgen to compile a td file 3########################################################## 4define transform-td-to-out 5$(if $(LOCAL_IS_HOST_MODULE), \ 6 $(call transform-host-td-to-out,$(1)), \ 7 $(call transform-device-td-to-out,$(1))) 8endef 9 10########################################################### 11## TableGen: Compile .td files to .inc. 12########################################################### 13ifeq ($(LOCAL_MODULE_CLASS),) 14 LOCAL_MODULE_CLASS := STATIC_LIBRARIES 15endif 16 17ifneq ($(strip $(TBLGEN_TABLES)),) 18 19intermediates := $(call local-intermediates-dir) 20tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES)) 21LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables) 22 23tblgen_source_dir := $(LOCAL_PATH) 24ifneq ($(TBLGEN_TD_DIR),) 25tblgen_source_dir := $(TBLGEN_TD_DIR) 26endif 27 28ifneq ($(filter %GenRegisterNames.inc,$(tblgen_gen_tables)),) 29$(intermediates)/%GenRegisterNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 30 $(call transform-td-to-out,register-enums) 31endif 32 33ifneq ($(filter %GenRegisterInfo.h.inc,$(tblgen_gen_tables)),) 34$(intermediates)/%GenRegisterInfo.h.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 35 $(call transform-td-to-out,register-desc-header) 36endif 37 38ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),) 39$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 40 $(call transform-td-to-out,register-desc) 41endif 42 43ifneq ($(filter %GenInstrNames.inc,$(tblgen_gen_tables)),) 44$(intermediates)/%GenInstrNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 45 $(call transform-td-to-out,instr-enums) 46endif 47 48ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),) 49$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 50 $(call transform-td-to-out,instr-desc) 51endif 52 53ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),) 54$(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 55 $(call transform-td-to-out,asm-writer) 56endif 57 58ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),) 59$(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 60 $(call transform-td-to-out,asm-writer -asmwriternum=1) 61endif 62 63ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),) 64$(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 65 $(call transform-td-to-out,asm-matcher) 66endif 67 68ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),) 69$(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 70 $(call transform-td-to-out,emitter) 71endif 72 73ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),) 74$(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 75 $(call transform-td-to-out,dag-isel) 76endif 77 78ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),) 79$(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 80 $(call transform-td-to-out,disassembler) 81endif 82 83ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),) 84$(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 85 $(call transform-td-to-out,enhanced-disassembly-info) 86endif 87 88ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),) 89$(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 90 $(call transform-td-to-out,fast-isel) 91endif 92 93ifneq ($(filter %GenSubtarget.inc,$(tblgen_gen_tables)),) 94$(intermediates)/%GenSubtarget.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 95 $(call transform-td-to-out,subtarget) 96endif 97 98ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),) 99$(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 100 $(call transform-td-to-out,callingconv) 101endif 102 103ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),) 104$(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 105 $(call transform-td-to-out,tgt_intrinsics) 106endif 107 108ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),) 109$(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN) 110 $(call transform-td-to-out,arm-decoder) 111endif 112 113endif 114