1; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2 2; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1 3 4@d2 = external global double 5@d3 = external global double 6 7define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone { 8entry: 9; CHECK-MIPS32R2: movn 10; CHECK-MIPS1: beq 11 %tobool = icmp ne i32 %s, 0 12 %cond = select i1 %tobool, i32 %f1, i32 %f0 13 ret i32 %cond 14} 15 16define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone { 17entry: 18; CHECK-MIPS32R2: movn.s 19; CHECK-MIPS1: beq 20 %tobool = icmp ne i32 %s, 0 21 %cond = select i1 %tobool, float %f0, float %f1 22 ret float %cond 23} 24 25define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone { 26entry: 27; CHECK-MIPS32R2: movn.d 28; CHECK-MIPS1: beq 29 %tobool = icmp ne i32 %s, 0 30 %cond = select i1 %tobool, double %f0, double %f1 31 ret double %cond 32} 33 34define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone { 35entry: 36; CHECK-MIPS32R2: c.eq.s 37; CHECK-MIPS32R2: movt.s 38; CHECK-MIPS1: c.eq.s 39; CHECK-MIPS1: bc1f 40 %cmp = fcmp oeq float %f2, %f3 41 %cond = select i1 %cmp, float %f0, float %f1 42 ret float %cond 43} 44 45define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone { 46entry: 47; CHECK-MIPS32R2: c.olt.s 48; CHECK-MIPS32R2: movt.s 49; CHECK-MIPS1: c.olt.s 50; CHECK-MIPS1: bc1f 51 %cmp = fcmp olt float %f2, %f3 52 %cond = select i1 %cmp, float %f0, float %f1 53 ret float %cond 54} 55 56define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone { 57entry: 58; CHECK-MIPS32R2: c.ule.s 59; CHECK-MIPS32R2: movf.s 60; CHECK-MIPS1: c.ule.s 61; CHECK-MIPS1: bc1t 62 %cmp = fcmp ogt float %f2, %f3 63 %cond = select i1 %cmp, float %f0, float %f1 64 ret float %cond 65} 66 67define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone { 68entry: 69; CHECK-MIPS32R2: c.ule.s 70; CHECK-MIPS32R2: movf.d 71; CHECK-MIPS1: c.ule.s 72; CHECK-MIPS1: bc1t 73 %cmp = fcmp ogt float %f2, %f3 74 %cond = select i1 %cmp, double %f0, double %f1 75 ret double %cond 76} 77 78define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone { 79entry: 80; CHECK-MIPS32R2: c.eq.d 81; CHECK-MIPS32R2: movt.d 82; CHECK-MIPS1: c.eq.d 83; CHECK-MIPS1: bc1f 84 %cmp = fcmp oeq double %f2, %f3 85 %cond = select i1 %cmp, double %f0, double %f1 86 ret double %cond 87} 88 89define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone { 90entry: 91; CHECK-MIPS32R2: c.olt.d 92; CHECK-MIPS32R2: movt.d 93; CHECK-MIPS1: c.olt.d 94; CHECK-MIPS1: bc1f 95 %cmp = fcmp olt double %f2, %f3 96 %cond = select i1 %cmp, double %f0, double %f1 97 ret double %cond 98} 99 100define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone { 101entry: 102; CHECK-MIPS32R2: c.ule.d 103; CHECK-MIPS32R2: movf.d 104; CHECK-MIPS1: c.ule.d 105; CHECK-MIPS1: bc1t 106 %cmp = fcmp ogt double %f2, %f3 107 %cond = select i1 %cmp, double %f0, double %f1 108 ret double %cond 109} 110 111define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone { 112entry: 113; CHECK-MIPS32R2: c.ule.d 114; CHECK-MIPS32R2: movf.s 115; CHECK-MIPS1: c.ule.d 116; CHECK-MIPS1: bc1t 117 %cmp = fcmp ogt double %f2, %f3 118 %cond = select i1 %cmp, float %f0, float %f1 119 ret float %cond 120} 121 122define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { 123entry: 124; CHECK-MIPS32R2: c.eq.s 125; CHECK-MIPS32R2: movt 126; CHECK-MIPS1: c.eq.s 127; CHECK-MIPS1: bc1f 128 %cmp = fcmp oeq float %f2, %f3 129 %cond = select i1 %cmp, i32 %f0, i32 %f1 130 ret i32 %cond 131} 132 133define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { 134entry: 135; CHECK-MIPS32R2: c.olt.s 136; CHECK-MIPS32R2: movt 137; CHECK-MIPS1: c.olt.s 138; CHECK-MIPS1: bc1f 139 %cmp = fcmp olt float %f2, %f3 140 %cond = select i1 %cmp, i32 %f0, i32 %f1 141 ret i32 %cond 142} 143 144define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { 145entry: 146; CHECK-MIPS32R2: c.ule.s 147; CHECK-MIPS32R2: movf 148; CHECK-MIPS1: c.ule.s 149; CHECK-MIPS1: bc1t 150 %cmp = fcmp ogt float %f2, %f3 151 %cond = select i1 %cmp, i32 %f0, i32 %f1 152 ret i32 %cond 153} 154 155define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly { 156entry: 157; CHECK-MIPS32R2: c.eq.d 158; CHECK-MIPS32R2: movt 159; CHECK-MIPS1: c.eq.d 160; CHECK-MIPS1: bc1f 161 %tmp = load double* @d2, align 8, !tbaa !0 162 %tmp1 = load double* @d3, align 8, !tbaa !0 163 %cmp = fcmp oeq double %tmp, %tmp1 164 %cond = select i1 %cmp, i32 %f0, i32 %f1 165 ret i32 %cond 166} 167 168define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly { 169entry: 170; CHECK-MIPS32R2: c.olt.d 171; CHECK-MIPS32R2: movt 172; CHECK-MIPS1: c.olt.d 173; CHECK-MIPS1: bc1f 174 %tmp = load double* @d2, align 8, !tbaa !0 175 %tmp1 = load double* @d3, align 8, !tbaa !0 176 %cmp = fcmp olt double %tmp, %tmp1 177 %cond = select i1 %cmp, i32 %f0, i32 %f1 178 ret i32 %cond 179} 180 181define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly { 182entry: 183; CHECK-MIPS32R2: c.ule.d 184; CHECK-MIPS32R2: movf 185; CHECK-MIPS1: c.ule.d 186; CHECK-MIPS1: bc1t 187 %tmp = load double* @d2, align 8, !tbaa !0 188 %tmp1 = load double* @d3, align 8, !tbaa !0 189 %cmp = fcmp ogt double %tmp, %tmp1 190 %cond = select i1 %cmp, i32 %f0, i32 %f1 191 ret i32 %cond 192} 193 194!0 = metadata !{metadata !"double", metadata !1} 195!1 = metadata !{metadata !"omnipotent char", metadata !2} 196!2 = metadata !{metadata !"Simple C/C++ TBAA", null} 197