1; RUN: llc < %s -march=ptx32 | FileCheck %s 2 3; preds 4; (note: we convert back to i32 to return) 5 6define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) { 7; CHECK: setp.gt.u16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0 8; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}}; 9; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]]; 10; CHECK-NEXT: ret; 11 %a = trunc i16 %x to i1 12 %b = and i1 %a, %y 13 %c = zext i1 %b to i32 14 ret i32 %c 15} 16 17define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) { 18; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0 19; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}}; 20; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]]; 21; CHECK-NEXT: ret; 22 %a = trunc i32 %x to i1 23 %b = and i1 %a, %y 24 %c = zext i1 %b to i32 25 ret i32 %c 26} 27 28define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) { 29; CHECK: setp.gt.u64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0 30; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}}; 31; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]]; 32; CHECK-NEXT: ret; 33 %a = trunc i64 %x to i1 34 %b = and i1 %a, %y 35 %c = zext i1 %b to i32 36 ret i32 %c 37} 38 39define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) { 40; CHECK: setp.gt.f32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0 41; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}}; 42; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]]; 43; CHECK-NEXT: ret; 44 %a = fptoui float %x to i1 45 %b = and i1 %a, %y 46 %c = zext i1 %b to i32 47 ret i32 %c 48} 49 50define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) { 51; CHECK: setp.gt.f64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0 52; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}}; 53; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]]; 54; CHECK-NEXT: ret; 55 %a = fptoui double %x to i1 56 %b = and i1 %a, %y 57 %c = zext i1 %b to i32 58 ret i32 %c 59} 60 61; i16 62 63define ptx_device i16 @cvt_i16_preds(i1 %x) { 64; CHECK: selp.u16 rh{{[0-9]+}}, 1, 0, p{{[0-9]+}}; 65; CHECK-NEXT: ret; 66 %a = zext i1 %x to i16 67 ret i16 %a 68} 69 70define ptx_device i16 @cvt_i16_i32(i32 %x) { 71; CHECK: cvt.u16.u32 rh{{[0-9]+}}, r{{[0-9]+}}; 72; CHECK-NEXT: ret; 73 %a = trunc i32 %x to i16 74 ret i16 %a 75} 76 77define ptx_device i16 @cvt_i16_i64(i64 %x) { 78; CHECK: cvt.u16.u64 rh{{[0-9]+}}, rd{{[0-9]+}}; 79; CHECK-NEXT: ret; 80 %a = trunc i64 %x to i16 81 ret i16 %a 82} 83 84define ptx_device i16 @cvt_i16_f32(float %x) { 85; CHECK: cvt.rzi.u16.f32 rh{{[0-9]+}}, r{{[0-9]+}}; 86; CHECK-NEXT: ret; 87 %a = fptoui float %x to i16 88 ret i16 %a 89} 90 91define ptx_device i16 @cvt_i16_f64(double %x) { 92; CHECK: cvt.rzi.u16.f64 rh{{[0-9]+}}, rd{{[0-9]+}}; 93; CHECK-NEXT: ret; 94 %a = fptoui double %x to i16 95 ret i16 %a 96} 97 98; i32 99 100define ptx_device i32 @cvt_i32_preds(i1 %x) { 101; CHECK: selp.u32 r{{[0-9]+}}, 1, 0, p{{[0-9]+}}; 102; CHECK-NEXT: ret; 103 %a = zext i1 %x to i32 104 ret i32 %a 105} 106 107define ptx_device i32 @cvt_i32_i16(i16 %x) { 108; CHECK: cvt.u32.u16 r{{[0-9]+}}, rh{{[0-9]+}}; 109; CHECK-NEXT: ret; 110 %a = zext i16 %x to i32 111 ret i32 %a 112} 113 114define ptx_device i32 @cvt_i32_i64(i64 %x) { 115; CHECK: cvt.u32.u64 r{{[0-9]+}}, rd{{[0-9]+}}; 116; CHECK-NEXT: ret; 117 %a = trunc i64 %x to i32 118 ret i32 %a 119} 120 121define ptx_device i32 @cvt_i32_f32(float %x) { 122; CHECK: cvt.rzi.u32.f32 r{{[0-9]+}}, r{{[0-9]+}}; 123; CHECK-NEXT: ret; 124 %a = fptoui float %x to i32 125 ret i32 %a 126} 127 128define ptx_device i32 @cvt_i32_f64(double %x) { 129; CHECK: cvt.rzi.u32.f64 r{{[0-9]+}}, rd{{[0-9]+}}; 130; CHECK-NEXT: ret; 131 %a = fptoui double %x to i32 132 ret i32 %a 133} 134 135; i64 136 137define ptx_device i64 @cvt_i64_preds(i1 %x) { 138; CHECK: selp.u64 rd{{[0-9]+}}, 1, 0, p{{[0-9]+}}; 139; CHECK-NEXT: ret; 140 %a = zext i1 %x to i64 141 ret i64 %a 142} 143 144define ptx_device i64 @cvt_i64_i16(i16 %x) { 145; CHECK: cvt.u64.u16 rd{{[0-9]+}}, rh{{[0-9]+}}; 146; CHECK-NEXT: ret; 147 %a = zext i16 %x to i64 148 ret i64 %a 149} 150 151define ptx_device i64 @cvt_i64_i32(i32 %x) { 152; CHECK: cvt.u64.u32 rd{{[0-9]+}}, r{{[0-9]+}}; 153; CHECK-NEXT: ret; 154 %a = zext i32 %x to i64 155 ret i64 %a 156} 157 158define ptx_device i64 @cvt_i64_f32(float %x) { 159; CHECK: cvt.rzi.u64.f32 rd{{[0-9]+}}, r{{[0-9]+}}; 160; CHECK-NEXT: ret; 161 %a = fptoui float %x to i64 162 ret i64 %a 163} 164 165define ptx_device i64 @cvt_i64_f64(double %x) { 166; CHECK: cvt.rzi.u64.f64 rd{{[0-9]+}}, rd{{[0-9]+}}; 167; CHECK: ret; 168 %a = fptoui double %x to i64 169 ret i64 %a 170} 171 172; f32 173 174define ptx_device float @cvt_f32_preds(i1 %x) { 175; CHECK: selp.f32 r{{[0-9]+}}, 0F3F800000, 0F00000000, p{{[0-9]+}}; 176; CHECK-NEXT: ret; 177 %a = uitofp i1 %x to float 178 ret float %a 179} 180 181define ptx_device float @cvt_f32_i16(i16 %x) { 182; CHECK: cvt.rn.f32.u16 r{{[0-9]+}}, rh{{[0-9]+}}; 183; CHECK-NEXT: ret; 184 %a = uitofp i16 %x to float 185 ret float %a 186} 187 188define ptx_device float @cvt_f32_i32(i32 %x) { 189; CHECK: cvt.rn.f32.u32 r{{[0-9]+}}, r{{[0-9]+}}; 190; CHECK-NEXT: ret; 191 %a = uitofp i32 %x to float 192 ret float %a 193} 194 195define ptx_device float @cvt_f32_i64(i64 %x) { 196; CHECK: cvt.rn.f32.u64 r{{[0-9]+}}, rd{{[0-9]+}}; 197; CHECK-NEXT: ret; 198 %a = uitofp i64 %x to float 199 ret float %a 200} 201 202define ptx_device float @cvt_f32_f64(double %x) { 203; CHECK: cvt.rn.f32.f64 r{{[0-9]+}}, rd{{[0-9]+}}; 204; CHECK-NEXT: ret; 205 %a = fptrunc double %x to float 206 ret float %a 207} 208 209; f64 210 211define ptx_device double @cvt_f64_preds(i1 %x) { 212; CHECK: selp.f64 rd{{[0-9]+}}, 0D3F80000000000000, 0D0000000000000000, p{{[0-9]+}}; 213; CHECK-NEXT: ret; 214 %a = uitofp i1 %x to double 215 ret double %a 216} 217 218define ptx_device double @cvt_f64_i16(i16 %x) { 219; CHECK: cvt.rn.f64.u16 rd{{[0-9]+}}, rh{{[0-9]+}}; 220; CHECK-NEXT: ret; 221 %a = uitofp i16 %x to double 222 ret double %a 223} 224 225define ptx_device double @cvt_f64_i32(i32 %x) { 226; CHECK: cvt.rn.f64.u32 rd{{[0-9]+}}, r{{[0-9]+}}; 227; CHECK-NEXT: ret; 228 %a = uitofp i32 %x to double 229 ret double %a 230} 231 232define ptx_device double @cvt_f64_i64(i64 %x) { 233; CHECK: cvt.rn.f64.u64 rd{{[0-9]+}}, rd{{[0-9]+}}; 234; CHECK-NEXT: ret; 235 %a = uitofp i64 %x to double 236 ret double %a 237} 238 239define ptx_device double @cvt_f64_f32(float %x) { 240; CHECK: cvt.f64.f32 rd{{[0-9]+}}, r{{[0-9]+}}; 241; CHECK-NEXT: ret; 242 %a = fpext float %x to double 243 ret double %a 244} 245