1; RUN: opt %s -sccp -S | FileCheck %s 2 3 4; PR6940 5define double @test1() { 6 %t = sitofp i32 undef to double 7 ret double %t 8; CHECK: @test1 9; CHECK: ret double 0.0 10} 11 12 13; rdar://7832370 14; Check that lots of stuff doesn't get turned into undef. 15define i32 @test2() nounwind readnone ssp { 16; CHECK: @test2 17init: 18 br label %control.outer.outer 19 20control.outer.loopexit.us-lcssa: ; preds = %control 21 br label %control.outer.loopexit 22 23control.outer.loopexit: ; preds = %control.outer.loopexit.us-lcssa.us, %control.outer.loopexit.us-lcssa 24 br label %control.outer.outer.backedge 25 26control.outer.outer: ; preds = %control.outer.outer.backedge, %init 27 %switchCond.0.ph.ph = phi i32 [ 2, %init ], [ 3, %control.outer.outer.backedge ] ; <i32> [#uses=2] 28 %i.0.ph.ph = phi i32 [ undef, %init ], [ %i.0.ph.ph.be, %control.outer.outer.backedge ] ; <i32> [#uses=1] 29 %tmp4 = icmp eq i32 %i.0.ph.ph, 0 ; <i1> [#uses=1] 30 br i1 %tmp4, label %control.outer.outer.split.us, label %control.outer.outer.control.outer.outer.split_crit_edge 31 32control.outer.outer.control.outer.outer.split_crit_edge: ; preds = %control.outer.outer 33 br label %control.outer 34 35control.outer.outer.split.us: ; preds = %control.outer.outer 36 br label %control.outer.us 37 38control.outer.us: ; preds = %bb3.us, %control.outer.outer.split.us 39 %A.0.ph.us = phi i32 [ %switchCond.0.us, %bb3.us ], [ 4, %control.outer.outer.split.us ] ; <i32> [#uses=2] 40 %switchCond.0.ph.us = phi i32 [ %A.0.ph.us, %bb3.us ], [ %switchCond.0.ph.ph, %control.outer.outer.split.us ] ; <i32> [#uses=1] 41 br label %control.us 42 43bb3.us: ; preds = %control.us 44 br label %control.outer.us 45 46bb0.us: ; preds = %control.us 47 br label %control.us 48 49; CHECK: control.us: ; preds = %bb0.us, %control.outer.us 50; CHECK-NEXT: %switchCond.0.us = phi i32 51; CHECK-NEXT: switch i32 %switchCond.0.us 52control.us: ; preds = %bb0.us, %control.outer.us 53 %switchCond.0.us = phi i32 [ %A.0.ph.us, %bb0.us ], [ %switchCond.0.ph.us, %control.outer.us ] ; <i32> [#uses=2] 54 switch i32 %switchCond.0.us, label %control.outer.loopexit.us-lcssa.us [ 55 i32 0, label %bb0.us 56 i32 1, label %bb1.us-lcssa.us 57 i32 3, label %bb3.us 58 i32 4, label %bb4.us-lcssa.us 59 ] 60 61control.outer.loopexit.us-lcssa.us: ; preds = %control.us 62 br label %control.outer.loopexit 63 64bb1.us-lcssa.us: ; preds = %control.us 65 br label %bb1 66 67bb4.us-lcssa.us: ; preds = %control.us 68 br label %bb4 69 70control.outer: ; preds = %bb3, %control.outer.outer.control.outer.outer.split_crit_edge 71 %A.0.ph = phi i32 [ %nextId17, %bb3 ], [ 4, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1] 72 %switchCond.0.ph = phi i32 [ 0, %bb3 ], [ %switchCond.0.ph.ph, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1] 73 br label %control 74 75control: ; preds = %bb0, %control.outer 76 %switchCond.0 = phi i32 [ %A.0.ph, %bb0 ], [ %switchCond.0.ph, %control.outer ] ; <i32> [#uses=2] 77 switch i32 %switchCond.0, label %control.outer.loopexit.us-lcssa [ 78 i32 0, label %bb0 79 i32 1, label %bb1.us-lcssa 80 i32 3, label %bb3 81 i32 4, label %bb4.us-lcssa 82 ] 83 84bb4.us-lcssa: ; preds = %control 85 br label %bb4 86 87bb4: ; preds = %bb4.us-lcssa, %bb4.us-lcssa.us 88 br label %control.outer.outer.backedge 89 90control.outer.outer.backedge: ; preds = %bb4, %control.outer.loopexit 91 %i.0.ph.ph.be = phi i32 [ 1, %bb4 ], [ 0, %control.outer.loopexit ] ; <i32> [#uses=1] 92 br label %control.outer.outer 93 94bb3: ; preds = %control 95 %nextId17 = add i32 %switchCond.0, -2 ; <i32> [#uses=1] 96 br label %control.outer 97 98bb0: ; preds = %control 99 br label %control 100 101bb1.us-lcssa: ; preds = %control 102 br label %bb1 103 104bb1: ; preds = %bb1.us-lcssa, %bb1.us-lcssa.us 105 ret i32 0 106} 107